 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| renesas 32-bit risc single-chip microcomputer m32r family / m32r/ecu series 32176 group 32 rev. 1.01 revision date: oct 31, 2003 user?s manual www.renesas.com before using this material, please visit our website to confirm that this is the most current document available. rej09b0067-0101z
keep safety first in your circuit designs! notes regarding these materials renesas technology corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. renesas technology corporation assumes no responsibility for any damage, or infringe- ment of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that custom- ers contact renesas technology corporation or an authorized renesas technology cor- poration product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any dam- age, liability or other loss resulting from the information contained herein. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is poten- tially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product con- tained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. please contact renesas technology corporation for further details on these materials or the products contained therein. revision history rev. date description page summary (1/1) 32176 group user?s manual 1.01 oct 31, 2003 first edition issued ? guide to understanding the register table (1) bit number: indicates a register?s bit number. (2) register border: the registers enclosed with thick border lines must be accessed in halfwords or words. (3) status after reset: the initial state of each register after reset is indicated in hexadecimal or binary. (4) status after reset: the initial state of each register after reset is indicated bitwise. 0: this bit is ?0? after reset. 1: this bit is ?1? after reset. ?: this bit is undefined after reset. (5) the shaded bits mean that they have no functions assigned. (6) read conditions: r: this bit can be accessed for read. ?: the value read from this bit is undefined. (reading this bit has no effect.) 0: the value read from this bit is always ?0?. 1: the value read from this bit is always ?1?. (7) write conditions: w: this bit can be accessed for write. n: this bit is write protected. 0: to write to this bit, always write ?0?. 1: to write to this bit, always write ?1?. ?: writing to this bit has no effect. (it does not matter whether this bit is set to ?0? or ?1? by writing in software.) note: care must be taken when writing to this bit. see note in each register table. xxxregister(xxx) (1) table of contents chapter 1 overview 1.1 outline of the 32176 group ---------------------------------------------------------------------------------------------- 1- 2 1.1.1 m32r family cpu core -------------------------------------------------------------------------------------- 1-2 1.1.2 built-in multiplier/accumulator ------------------------------------------------------------------------------- 1-2 1.1.3 built-in flash memory and ram ---------------------------------------------------------------------------- 1-3 1.1.4 built-in clock frequency multiplier ------------------------------------------------------------------------- 1-3 1.1.5 powerful built-in peripheral functions --------------------------------------------------------------------- 1-4 1.1.6 product list of the 32176 group ---------------------------------------------------------------------------- 1-4 1.2 block diagram ------------------------------------------------------------------------------------------------------------- - 1-5 1.3 pin functions ------------------------------------------------------------------------------------------------------------- -- 1-8 1.4 pin assignments ----------------------------------------------------------------------------------------------------------- 1-13 chapter 2 cpu 2.1 cpu registers ------------------------------------------------------------------------------------------------------------- 2-2 2.2 general-purpose registers --------------------------------------------------------------------------------------------- 2-2 2.3 control registers --------------------------------------------------------------------------------------------------------- - 2-3 2.3.1 processor status word register: psw (cr0) ---------------------------------------------------------- 2-4 2.3.2 condition bit register: cbr (cr1) ------------------------------------------------------------------------- 2-5 2.3.3 interrupt stack pointer: spi (cr2) and user stack pointer: spu (cr3) ------------------------- 2-5 2.3.4 backup pc: bpc (cr6) -------------------------------------------------------------------------------------- 2-5 2.4 accumulator --------------------------------------------------------------------------------------------------------------- - 2-6 2.5 program counter ---------------------------------------------------------------------------------------------------------- 2 -6 2.6 data formats -------------------------------------------------------------------------------------------------------------- - 2-7 2.6.1 data types ------------------------------------------------------------------------------------------------------- 2-7 2.6.2 data formats ---------------------------------------------------------------------------------------------------- 2-8 2.7 supplementary explanation for lock and unlock instruction execution --------------------------------- 2-14 chapter 3 address space 3.1 outline of the address space ------------------------------------------------------------------------------------------ 3-2 3.2 operation modes ---------------------------------------------------------------------------------------------------------- 3 -6 3.3 internal rom and external extension areas ------------------------------------------------------------------------ 3-8 3.3.1 internal rom area --------------------------------------------------------------------------------------------- 3-8 3.3.2 external extension area -------------------------------------------------------------------------------------- 3-8 3.4 internal ram and sfr areas ------------------------------------------------------------------------------------------ 3-9 3.4.1 internal ram area --------------------------------------------------------------------------------------------- 3-9 3.4.2 sfr (special function register) area -------------------------------------------------------------------- 3-9 3.5 eit vector entry ---------------------------------------------------------------------------------------------------------- - 3-33 3.6 icu vector table ---------------------------------------------------------------------------------------------------------- 3-34 3.7 notes about address space -------------------------------------------------------------------------------------------- 3-36 chapter 4 eit 4.1 outline of eit ------------------------------------------------------------------------------------------------------------ --- 4-2 4.2 eit events ---------------------------------------------------------------------------------------------------------------- -- 4-3 (2) 4.2.1 exception --------------------------------------------------------------------------------------------------------- 4-3 4.2.2 interrupt ----------------------------------------------------------------------------------------------------------- 4-3 4.2.3 trap ---------------------------------------------------------------------------------------------------------------- 4-3 4.3 eit processing procedure ---------------------------------------------------------------------------------------------- 4-4 4.4 eit processing mechanism --------------------------------------------------------------------------------------------- 4-6 4.5 acceptance of eit events ----------------------------------------------------------------------------------------------- 4-7 4.6 saving and restoring the pc and psw ----------------------------------------------------------------------------- 4-7 4.7 eit vector entry ---------------------------------------------------------------------------------------------------------- - 4-9 4.8 exception processing ---------------------------------------------------------------------------------------------------- 4- 10 4.8.1 reserved instruction exception (rie) --------------------------------------------------------------------- 4-10 4.8.2 address exception (ae) -------------------------------------------------------------------------------------- 4-12 4.9 interrupt processing ------------------------------------------------------------------------------------------------------ 4-14 4.9.1 reset interrupt (ri) -------------------------------------------------------------------------------------------- 4-14 4.9.2 system break interrupt (sbi) -------------------------------------------------------------------------------- 4-15 4.9.3 external interrupt (ei) ----------------------------------------------------------------------------------------- 4-17 4.10 trap pr ocessing ---------------------------------------------------------------------------------------------------------- 4-19 4.10.1 trap ---------------------------------------------------------------------------------------------------------------- 4-19 4.11 eit priority levels ------------------------------------------------------------------------------------------------------ - 4-21 4.12 example of eit processing ------------------------------------------------------------------------------------------- 4-22 4.13 precautions on eit ------------------------------------------------------------------------------------------------------ 4 -24 chapter 5 interrupt controller (icu) 5.1 outline of the interrupt controller --------------------------------------------------------------------------------------- 5-2 5.2 icu related registers --------------------------------------------------------------------------------------------------- 5- 4 5.2.1 interrupt ve ctor registe r ------------------------------------------------------------------------------------- 5-5 5.2.2 interrupt request mask register --------------------------------------------------------------------------- 5-6 5.2.3 sbi (system break interrupt) control register --------------------------------------------------------- 5-7 5.2.4 interrupt control registers ----------------------------------------------------------------------------------- 5-8 5.3 interrupt request sources in internal peripheral i/o ------------------------------------------------------------- 5-11 5.4 icu ve ctor table ---------------------------------------------------------------------------------------------------------- 5-12 5.5 description of interrupt operation ------------------------------------------------------------------------------------- 5-1 3 5.5.1 acceptance of internal peripheral i/o interrupts ------------------------------------------------------- 5-13 5.5.2 processing by internal peripheral i/o interrupt handlers -------------------------------------------- 5-15 5.6 description of system break interrupt (sbi) o peration ---------------------------------------------------------- 5-18 5.6.1 acceptance of sbi --------------------------------------------------------------------------------------------- 5-18 5.6.2 sbi processing by handler ---------------------------------------------------------------------------------- 5-18 chapter 6 internal memory 6.1 outline of the internal memory ----------------------------------------------------------------------------------------- 6-2 6.2 internal ram -------------------------------------------------------------------------------------------------------------- -- 6-2 6.3 internal flash memory --------------------------------------------------------------------------------------------------- 6- 2 6.4 registers associated with the internal flash memory ----------------------------------------------------------- 6-6 6.4.1 flash mode register ------------------------------------------------------------------------------------------ 6-7 6.4.2 flash stat us register ------------------------------------------------------------------------------------------ 6-8 6.4.3 flash control registers --------------------------------------------------------------------------------------- 6-9 6.4.4 virtual flash l bank registers ------------------------------------------------------------------------------ 6-15 6.4.5 virtual flash s bank registers ------------------------------------------------------------------------------ 6-16 6.5 programming the internal flash memory ---------------------------------------------------------------------------- 6-17 (3) 6.5.1 outline of internal flash memory programming --------------------------------------------------------- 6-17 6.5.2 controlling operation modes during flash programming -------------------------------------------- 6-23 6.5.3 procedure for programming/erasing the internal flash memory ---------------------------------- 6-26 6.5.4 flash programming time (referenc e) -------------------------------------------------------------------- 6-34 6.6 virtual flash emulation function -------------------------------------------------------------------------------------- 6-36 6.6.1 virtual flash emulation area -------------------------------------------------------------------------------- 6-37 6.6.2 entering virtual flash emulation mode ------------------------------------------------------------------- 6-44 6.6.3 application example of virtual flash emulation mode ------------------------------------------------ 6-45 6.7 connecting to a serial programmer (csio mode) ----------------------------------------------------------------- 6-47 6.8 internal flash memory protect function ----------------------------------------------------------------------------- 6-49 6.9 precautions to be taken when rewriting the internal flash memory -------------------------------------- 6-50 chapter 7 reset 7.1 outline of reset ---------------------------------------------------------------------------------------------------------- -- 7-2 7.2 reset operation ----------------------------------------------------------------------------------------------------------- 7-2 7.2.1 reset at power-on --------------------------------------------------------------------------------------------- 7-3 7.2.2 reset during operation ---------------------------------------------------------------------------------------- 7-3 7.2.3 reset vector relocation during flash programming --------------------------------------------------- 7-3 7.3 internal state immediately after exiting reset ---------------------------------------------------------------------- 7-4 7.4 things to be considered after exiting reset ------------------------------------------------------------------------ 7-4 chapter 8 input/output ports and pin functions 8.1 outline of input/output ports ------------------------------------------------------------------------------------------- 8- 2 8.2 selecting pin functions -------------------------------------------------------------------------------------------------- 8 -3 8.3 input/output port related registers ---------------------------------------------------------------------------------- 8-5 8.3.1 port data registers -------------------------------------------------------------------------------------------- 8-7 8.3.2 port direction registers -------------------------------------------------------------------------------------- 8-8 8.3.3 port operation mode registers ----------------------------------------------------------------------------- 8-9 8.3.4 port peripheral function select register ----------------------------------------------------------------- 8-14 8.3.5 port input special function control register ------------------------------------------------------------ 8-15 8.4 port input level switching function ---------------------------------------------------------------------------------- 8-18 8.5 port peripheral circuits -------------------------------------------------------------------------------------------------- 8-20 8.6 precautions on input/output ports ------------------------------------------------------------------------------------ 8-25 chapter 9 dmac 9.1 outline of the dmac ------------------------------------------------------------------------------------------------------ 9 -2 9.2 dmac related registers ------------------------------------------------------------------------------------------------ 9-4 9.2.1 dma channel control registers --------------------------------------------------------------------------- 9-6 9.2.2 dma software request generation registers ---------------------------------------------------------- 9-12 9.2.3 dma source address registers ---------------------------------------------------------------------------- 9-13 9.2.4 dma destination address registers ---------------------------------------------------------------------- 9-14 9.2.5 dma transfer count registers ----------------------------------------------------------------------------- 9-15 9.2.6 dma interrupt related registers --------------------------------------------------------------------------- 9-16 9.3 functional description of the dmac ---------------------------------------------------------------------------------- 9-22 9.3.1 dma transfer request sources --------------------------------------------------------------------------- 9-22 9.3.2 dma transfer processing procedure --------------------------------------------------------------------- 9-25 9.3.3 starting dma ---------------------------------------------------------------------------------------------------- 9-26 (4) 9.3.4 dma channel priority ------------------------------------------------------------------------------------------ 9-26 9.3.5 gaining and releasing control of the internal bus ------------------------------------------------------ 9-26 9.3.6 transfer units --------------------------------------------------------------------------------------------------- 9-27 9.3.7 transfer counts ------------------------------------------------------------------------------------------------ 9-27 9.3.8 address space -------------------------------------------------------------------------------------------------- 9-27 9.3.9 transfer operation --------------------------------------------------------------------------------------------- 9-27 9.3.10 end of dma and interrupt ------------------------------------------------------------------------------------ 9-30 9.3.11 each register status after completion of dma transfer -------------------------------------------- 9-30 9.4 precautions about the dmac ------------------------------------------------------------------------------------------ 9-31 chapter 10 multijunction timers 10.1 outline of multijunction timers ---------------------------------------------------------------------------------------- 10 -2 10.2 common units of multijunction timers ----------------------------------------------------------------------------- 10-7 10.2.1 mjt common unit register map ------------------------------------------------------------------------- 10-8 10.2.2 prescaler unit -------------------------------------------------------------------------------------------------- 10-9 10.2.3 clock bus and input/output event bus control unit ------------------------------------------------- 10-10 10.2.4 input processing control unit ------------------------------------------------------------------------------ 10-14 10.2.5 output flip-flop control unit -------------------------------------------------------------------------------- 10-20 10.2.6 interrupt control unit ----------------------------------------------------------------------------------------- 10-25 10.3 top (output-related 16-bit timer) --------------------------------------------------------------------------------- 10-42 10.3.1 outline of top -------------------------------------------------------------------------------------------------- 10-42 10.3.2 outline of each mode of top ------------------------------------------------------------------------------- 10-44 10.3.3 top related register map ---------------------------------------------------------------------------------- 10-46 10.3.4 top control r egisters ---------------------------------------------------------------------------------------- 10-48 10.3.5 top counters (top0ct?top10ct) --------------------------------------------------------------------- 10-53 10.3.6 top reload registers (top0rl?top10rl) ---------------------------------------------------------- 10-54 10.3.7 top correction registers (top0cc?top10cc) ----------------------------------------------------- 10-55 10.3.8 top enable control registers ------------------------------------------------------------------------------ 10-56 10.3.9 operation in top single-shot output mode (with correction function) -------------------------- 10-58 10.3.10 operation in top delayed single-shot output mode (with correction function) -------------- 10-64 10.3.11 operation in top continuous output mode (without correction function) --------------------- 10-69 10.4 tio (input/output-related 16-bit timer) --------------------------------------------------------------------------- 10-72 10.4.1 outline of tio --------------------------------------------------------------------------------------------------- 10-72 10.4.2 outline of each mode of tio -------------------------------------------------------------------------------- 10-74 10.4.3 tio related register map ----------------------------------------------------------------------------------- 10-77 10.4.4 tio control registers ----------------------------------------------------------------------------------------- 10-79 10.4.5 tio counters ( tio0ct?tio9ct) -------------------------------------------------------------------------- 10-87 10.4.6 tio reload 0/ measure registers (tio0rl0?tio9rl0) -------------------------------------------- 10-88 10.4.7 tio reload 1 registers (tio0rl1?tio9rl1) ---------------------------------------------------------- 10-89 10.4.8 tio enable control registers ------------------------------------------------------------------------------- 10-90 10.4.9 operation in tio measure free-run/clear input modes ----------------------------------------------- 10-92 10.4.10 operation in tio noise processing input mode -------------------------------------------------------- 10-94 10.4.11 operation in tio pwm output mode --------------------------------------------------------------------- 10-95 10.4.12 operation in tio single-shot output mode (without correction function) ----------------------- 10-98 10.4.13 operation in tio delayed single-shot output mode (without correction function) ----------- 10-100 10.4.14 operation in tio continuous output mode (without correction function) ----------------------- 10-102 10.5 tms (input-related 16-bit timer) ----------------------------------------------------------------------------------- 10-104 10.5.1 outline of tms -------------------------------------------------------------------------------------------------- 10-104 (5) 10.5.2 outline of tms operation ------------------------------------------------------------------------------------- 10-104 10.5.3 tms related register map ----------------------------------------------------------------------------------- 10-106 10.5.4 tms control registers ---------------------------------------------------------------------------------------- 10-107 10.5.5 tms counters (tms0ct, tms1ct) ---------------------------------------------------------------------- 10-108 10.5.6 tms measure registers (tms0mr3?0, tms1mr3?0) ---------------------------------------------- 10-108 10.5.7 operation of tms measure input -------------------------------------------------------------------------- 10-109 10.6 tml (input-related 32-bit timer) ----------------------------------------------------------------------------------- 10-110 10.6.1 outline of tml -------------------------------------------------------------------------------------------------- 10-110 10.6.2 outline of tml operation ------------------------------------------------------------------------------------ 10-111 10.6.3 tml related register map ---------------------------------------------------------------------------------- 10-111 10.6.4 tml control registers ---------------------------------------------------------------------------------------- 10-112 10.6.5 tml counters --------------------------------------------------------------------------------------------------- 10-113 10.6.6 tml measure registers -------------------------------------------------------------------------------------- 10-114 10.6.7 operation of tml measure input --------------------------------------------------------------------------- 10-116 chapter 11 a-d converter 11.1 outline of a-d converter ----------------------------------------------------------------------------------------------- 11 -2 11.1.1 conversion modes --------------------------------------------------------------------------------------------- 11-5 11.1.2 operation modes ----------------------------------------------------------------------------------------------- 11-5 11.1.3 special operation modes ------------------------------------------------------------------------------------ 11-8 11.1.4 a-d converter interrupt and dma transfer requests ------------------------------------------------ 11-11 11.1.5 sample-and-hold function ----------------------------------------------------------------------------------- 11-11 11.2 a-d converter related registers ------------------------------------------------------------------------------------ 11-12 11.2.1 a-d single mode register 0 --------------------------------------------------------------------------------- 11-14 11.2.2 a-d single mode register 1 --------------------------------------------------------------------------------- 11-16 11.2.3 a-d scan mode register 0 ---------------------------------------------------------------------------------- 11-18 11.2.4 a-d scan mode register 1 ---------------------------------------------------------------------------------- 11-20 11.2.5 a-d conversion speed control register ----------------------------------------------------------------- 11-22 11.2.6 a-d disconnection detection assist function control register ------------------------------------ 11-23 11.2.7 a-d disconnection detection assist method select register --------------------------------------- 11-24 11.2.8 a-d successive approximation register ----------------------------------------------------------------- 11-27 11.2.9 a-d comparate data register ------------------------------------------------------------------------------ 11-28 11.2.10 10-bit a-d data registers ------------------------------------------------------------------------------------ 11-29 11.2.11 8-bit a-d data registers -------------------------------------------------------------------------------------- 11-30 11.3 functional description of a-d converter --------------------------------------------------------------------------- 11-31 11.3.1 how to find analog input voltages ------------------------------------------------------------------------ 11-31 11.3.2 a-d conversion by successive approximation method ---------------------------------------------- 11-32 11.3.3 comparator operation ---------------------------------------------------------------------------------------- 11-33 11.3.4 calculating the a-d conversion time --------------------------------------------------------------------- 11-34 11.3.5 accuracy of a-d conversion -------------------------------------------------------------------------------- 11-37 11.4 inflow current bypass circuit ----------------------------------------------------------------------------------------- 11- 39 11.5 precautions on using a-d converter ------------------------------------------------------------------------------- 11-41 chapter 12 serial i/o 12.1 outline of serial i/o ---------------------------------------------------------------------------------------------------- - 12-2 12.2 serial i/o rela ted registers ------------------------------------------------------------------------------------------ 12- 5 12.2.1 sio interrupt related registers ---------------------------------------------------------------------------- 12-6 12.2.2 sio interrupt control registers ----------------------------------------------------------------------------- 12-9 (6) 12.2.3 sio transmit control registers ----------------------------------------------------------------------------- 12-13 12.2.4 sio transmit/receive mode registers -------------------------------------------------------------------- 12-15 12.2.5 sio transmit buffer registers ------------------------------------------------------------------------------ 12-18 12.2.6 sio receive buffer registers ------------------------------------------------------------------------------- 12-19 12.2.7 sio receive control registers ----------------------------------------------------------------------------- 12-20 12.2.8 sio baud rate registers ------------------------------------------------------------------------------------ 12-23 12.2.9 sio special mode registers -------------------------------------------------------------------------------- 12-24 12.3 transmit operation in csio mode ---------------------------------------------------------------------------------- 12-25 12.3.1 setting the csio baud rate --------------------------------------------------------------------------------- 12-25 12.3.2 initializing csio transmission ------------------------------------------------------------------------------ 12-26 12.3.3 starting csio transmission --------------------------------------------------------------------------------- 12-28 12.3.4 successive csio transmission ---------------------------------------------------------------------------- 12-28 12.3.5 processing at end of csio transmission --------------------------------------------------------------- 12-29 12.3.6 transmit interrupts --------------------------------------------------------------------------------------------- 12-29 12.3.7 transmit dma transfer request --------------------------------------------------------------------------- 12-29 12.3.8 example of csio transmit operation -------------------------------------------------------------------- 12-31 12.4 receive operation in csio mode ----------------------------------------------------------------------------------- 12-33 12.4.1 initialization for csio reception ---------------------------------------------------------------------------- 12-33 12.4.2 starting csio reception ------------------------------------------------------------------------------------- 12-35 12.4.3 processing at end of csio reception -------------------------------------------------------------------- 12-35 12.4.4 about successive reception -------------------------------------------------------------------------------- 12-36 12.4.5 flags showing the status of csio receive operation ----------------------------------------------- 12-37 12.4.6 example of csio receive operation --------------------------------------------------------------------- 12-38 12.5 precautions on using csio mode ----------------------------------------------------------------------------------- 12-40 12.6 transmit operation in uart mode --------------------------------------------------------------------------------- 12-41 12.6.1 setting the uart baud rate -------------------------------------------------------------------------------- 12-41 12.6.2 uart transmit/receive data formats ------------------------------------------------------------------- 12-41 12.6.3 initializing uart transmission ----------------------------------------------------------------------------- 12-43 12.6.4 starting uart transmission ------------------------------------------- ------------------------------------- 12-45 12.6.5 successive uart transmission --------------------------------------------------------------------------- 12-45 12.6.6 processing at end of uart transmission --------------------------------------------------------------- 12-45 12.6.7 transmit interrupts --------------------------------------------------------------------------------------------- 12-45 12.6.8 transmit dma transfer request --------------------------------------------------------------------------- 12-46 12.6.9 example of uart transmit operation ------------------------------------------------------------------- 12-47 12.7 receive operation in uart mode ---------------------------------------------------------------------------------- 12-49 12.7.1 initialization for uart reception --------------------------------------------------------------------------- 12-49 12.7.2 starting uart reception ------------------------------------------------------------------------------------ 12-51 12.7.3 processing at end of uart reception ------------------------------------------------------------------- 12-51 12.7.4 example of uart receive operation -------------------------------------------------------------------- 12-53 12.7.5 start bit detection during uart reception ------------------------------------------------------------- 12-55 12.8 fixed period clock output function -------------------------------------------------------------------------------- 12-56 12.9 precautions on using uart mode ---------------------------------------------------------------------------------- 12-57 chapter 13 can module 13.1 outline of the can module -------------------------------------------------------------------------------------------- 13-2 13.2 can module related registers -------------------------------------------------------------------------------------- 13-4 13.2.1 can control registers ---------------------------------------------------------------------------------------- 13-15 13.2.2 can status registers ----------------------------------------------------------------------------------------- 13-18 (7) 13.2.3 can fextended id registers ------------------------- ------------------------------------------------------- 13-21 13.2.4 can configuration registers -------------------------------------------------------------------------------- 13-22 13.2.5 can timestamp count registers -------------------------------------------------------------------------- 13-24 13.2.6 can error count registers ---------------------------------------------------------------------------------- 13-25 13.2.7 can baud rate prescalers ---------------------------------------------------------------------------------- 13-26 13.2.8 can interrupt related registers --------------------------------------------------------------------------- 13-27 13.2.9 can cause of error registers ------------------------------------------------------------------------------ 13-45 13.2.10 can mode registers ------------------------------------------------------------------------------------------ 13-47 13.2.11 can dm a transfer request select reg isters ----------------------------------------------------------- 13-48 13.2.12 can mask registers ------------------------------------------------------------------------------------------ 13-49 13.2.13 can single-shot mode control registers --------------------------------------------------------------- 13-53 13.2.14 can message slot control registers --------------------------------------------------------------------- 13-54 13.2.15 can message slots ------------------------------------------------------------------------------------------- 13-58 13.3 can protocol ------------------------------------------------------------------------------------------------------------- 13-73 13.3.1 can protocol frames ----------------------------------------------------------------------------------------- 13-73 13.3.2 data formats during can transmission/reception -------------------------------------------------- 13-74 13.3.3 can controller error states --------------------------------------------------------------------------------- 13-75 13.4 initializing the can module -------------------------------------------------------------------------------------------- 13 -76 13.4.1 initializing the can module ---------------------------------------------------------------------------------- 13-76 13.5 transmitting data frames --------------------------------------------------------------------------------------------- 13-7 9 13.5.1 data frame transmit procedure --------------------------------------------------------------------------- 13-79 13.5.2 data frame transmit operation ---------------------------------------------------------------------------- 13-80 13.5.3 transmit abort function -------------------------------------------------------------------------------------- 13-81 13.6 receiving data frames ------------------------------------------------------------------------------------------------ 13-8 2 13.6.1 data frame receive procedure ---------------------------------------------------------------------------- 13-82 13.6.2 data frame receive operation ----------------------------------------------------------------------------- 13-83 13.6.3 reading out received data frames ---------------------------------------------------------------------- 13-85 13.7 transmitting remote frames ---------------------------------------------------------------------------------------- 13-87 13.7.1 remote frame transmit procedure ----------------------------------------------------------------------- 13-87 13.7.2 remote frame transmit operation ----------------------------------------------------------------------- 13-88 13.7.3 reading out received data frames when set for remote frame transmission ------------ 13-90 13.8 receiving remote frames -------------------------------------------------------------------------------------------- 13-92 13.8.1 remote frame receive procedure ------------------------------------------------------------------------ 13-92 13.8.2 remote frame receive operation ------------------------------------------------------------------------ 13-93 13.9 precautions about can module -------------------------------------------------------------------------------------- 13-96 chapter 14 real time debugger (rtd) 14.1 outline of the real-time debugger (rtd) ------------------------------------------------------------------------ 14-2 14.2 pin functions of rtd ---------------------------------------------------------------------------------------------------- 1 4-3 14.3 rtd related register -------------------------------------------------------------------------------------------------- 14- 3 14.3.1 rtd write function disable register --------------------------------------------------------------------- 14-3 14.4 functional description of rtd ----------------------------------------------------------------------------------------- 14- 4 14.4.1 outline of rtd op eration ------------------------------------------------------------------------------------ 14-4 14.4.2 operation of rdr (real-time ram content output) ------------------------------------------------- 14-4 14.4.3 operation of wrr (ram content forcible rewrite) --------------------------------------------------- 14-6 14.4.4 operation of ver (continuous monitor) ----------------------------------------------------------------- 14-7 14.4.5 operation of vei (interrupt request) --------------------------------------------------------------------- 14-7 14.4.6 operation of rcv (recover from runaway) -------------------------------------------------------------- 14-8 (8) 14.4.7 method for setting a specified address when using rtd ------------------------------------------- 14-9 14.4.8 resetting rtd -------------------------------------------------------------------------------------------------- 14-10 14.5 typical connection with the host ------------------------------------------------------------------------------------ 14-11 chapter 15 external bus interface 15.1 external bus interface related signals ----------------------------------------------------------------------------- 15-2 15.2 external bus interface related registers ------------------------------------------------------------------------- 15-4 15.2.1 port operation mode register ------------------------------------------------------------------------------ 15-4 15.2.2 bus mode control register ---------------------------------------------------------------------------------- 15-5 15.3 read/write operations ------------------------------------------------------------------------------------------------- 15- 6 15.4 bus arbitration ---------------------------------------------------------------------------------------------------------- -- 15-12 15.5 typical connection of external extension memory ------------------------------------------------------------- 15-14 chapter 16 wait controller 16.1 outline of the wait controller ----------------------------------------------------------------------------------------- 16 -2 16.2 wait controller related register ------------------------------------------------------------------------------------- 16-4 16.2.1 wait cycles control register -------------------------------------------------------------------------------- 16-4 16.3 typical operation of the wait controller --------------------------------------------------------------------------- 16-5 chapter 17 ram backup mode 17.1 outline of ram backup mode ---------------------------------------------------------------------------------------- 17-2 17.2 example of ram backup when power is off -------------------------------------------------------------------------- 17-2 17.2.1 normal operating state --------------------------------------------------------------------------------------- 17-3 17.2.2 ram backup state --------------------------------------------------------------------------------------------- 17-4 17.3 example of ram backup for saving power consumption ---------------------------------------------------- 17-5 17.3.1 normal operating state --------------------------------------------------------------------------------------- 17-6 17.3.2 ram backup state --------------------------------------------------------------------------------------------- 17-7 17.3.3 precautions to be observed at power-on --------------------------------------------------------------- 17-8 17.4 exiting ram backup mode (wakeup) ------------------------------------------------------------------------------ 17-9 chapter 18 oscillator circuit 18.1 oscillator circuit ------------------------------------------------------------------------------------------------------- --- 18-2 18.1.1 example of an oscillator circuit ---------------------------------------------------------------------------- 18-2 18.1.2 xin oscillation stoppage detection function ------------------------------------------------------------ 18-3 18.1.3 oscillation drive capability select function ------------------------------------------------------------- 18-5 18.1.4 system clock output function ------------------------------------------------------------------------------ 18-7 18.1.5 oscillation stabilization time at power-on -------------------------------------------------------------- 18-7 18.2 clock generator circuit ------------------------------------------------------------------------------------------------ 18 -8 chapter 19 jtag 19.1 outlin e of jtag ---------------------------------------------------------------------------------------------------------- 19-2 19.2 configuration of jtag circuit ------------------------------------------------------------------------------------------ 19 -3 19.3 jtag registers ---------------------------------------------------------------------------------------------------------- 1 9-4 19.3.1 instruction register (jtagir) ------------------------------------------------------------------------------- 19-4 19.3.2 data register ---------------------------------------------------------------------------------------------------- 19-5 19.4 basic operation of jtag ---------------------------------------------------------------------------------------------- 19-6 19.4.1 outline of jtag operation ----------------------------------------------------------------------------------- 19-6 (9) 19.4.2 ir path sequence ---------------------------------------------------------------------------------------------- 19-8 19.4.3 dr path sequence -------------------------------------------------------------------------------------------- 19-9 19.4.4 inspecting and setting data registers -------------------------------------------------------------------- 19-10 19.5 boundary scan description language ----------------------------------------------------------------------------- 19-11 19.6 notes on board design when connecting jtag ---------------------------------------------------------------------- 19-12 19.7 processing pins when not using jtag ---------------------------------------------------------------------------- 19-13 chapter 20 power supply circuit 20.1 configuration of the power supply circuit -------------------------------------------------------------------------- 20-2 20.2 power-on sequence ---------------------------------------------------------------------------------------------------- 20-3 20.2.1 power-on sequence when not using ram backup -------------------------------------------------- 20-3 20.2.2 power-on sequence when using ram backup-------------------------------------------------------- 20-4 20.3 power-off sequence ---------------------------------------------------------------------------------------------------- 20- 5 20.3.1 power-off sequence when not using ram backup -------------------------------------------------- 20-5 20.3.2 power-off sequence when using ram backup ------------------------------------------------------- 20-6 chapter 21 electrical characteristics 21.1 absolute maximum ratings ------------------------------------------------------------------------------------------- 21-2 21.2 electrical characteristics when vcce = 5 v, f(xin) = 10 mhz ---------------------------------------------- 21-3 21.2.1 recommended operating conditions (when vcce = 5 v, f(xin) = 10 mhz) ------------------- 21-3 21.2.2 d.c. characteristics (when vcce = 5 v, f(xin) = 10 mhz) ----------------------------------------- 21-5 21.2.3 a-d conversion characteristics (when vcce = 5 v, f(xin) = 10 mhz) -------------------------- 21-6 21.3 electrical characteristics when vcce = 5 v, f(xin) = 8 mhz ------------------------------------------------ 21-7 21.3.1 recommended operating conditions (when vcce = 5 v, f(xin) = 8 mhz) -------------------- 21-7 21.3.2 d.c. characteristics (when vcce = 5 v, f(xin) = 8 mhz) ------------------------------------------- 21-9 21.3.3 a-d conversion characteristics (when vcce = 5 v, f(xin) = 8 mhz) ---------------------------- 21-10 21.4 electrical characteristics when vcce = 3.3 v, f(xin) = 10 mhz -------------------------------------------- 21-11 21.4.1 recommended operating conditions (when vcce = 3.3 v 0.3 v, f(xin) = 10 mhz) ------ 21-11 21.4.2 d.c. characteristics (when vcce = 3.3 v 0.3 v, f(xin) = 10 mhz) ---------------------------- 21-13 21.4.3 a-d conversion characteristics (when vcce = 3.3 v 0.3 v, f(xin) = 10 mhz) ------------- 21-14 21.5 electrical characteristics when vcce = 3.3 v, f(xin) = 8 mhz ---------------------------------------------- 21-15 21.5.1 recommended operating conditions (when vcce = 3.3 v 0.3 v f(xin) = 8 mhz) -------- 21-15 21.5.2 d.c. characteristics (when vcce = 3.3 v 0.3 v, f(xin) = 8 mhz) ------------------------------ 21-17 21.5.3 a-d conversion characteristics (when vcce = 3.3 v 0.3 v, f(xin) = 8 mhz) --------------- 21-18 21.6 flash memory related characteristics ----------------------------------------------------------------------------- 21-19 21.7 external capacitance for power supply ---------------------------------------------------------------------------- 21-20 21.8 a.c. characteristics (when vcce = 5 v) -------------------------------------------------------------------------- 21-20 21.8.1 timing requirements ----------------------------------------------------------------------------------------- 21-20 21.8.2 switching characteristics ------------------------------------------------------------------------------------- 21-24 21.8.3 a.c. characteristics -------------------------------------------------------------------------------------------- 21-27 21.9 a.c. characteristics (when vcce = 3.3 v) ----------------------------------------------------------------------- 21-36 21.9.1 timing requirements ----------------------------------------------------------------------------------------- 21-36 21.9.2 switching characteristics ------------------------------------------------------------------------------------- 21-40 21.9.3 a.c. characteristics -------------------------------------------------------------------------------------------- 21-43 chapter 22 typical characteristics to be written at a later time -------------------------------------------------------------------------------------------------- - 22-2 (10) appendix 1 mechanical specificaitons appendix 1.1 dimensional outline drawing -------------------------------------------------------------------- appendix 1-2 appendix 2 instruction processing time appendix 2.1 m32r/ecu instruction processing time ------------------------------------------------------ appendix 2-2 appendix 3 processing of unused pins appendix 3.1 example processing of unused pins --------------------------------------------------------- appendix 3-2 appendix 4 summary of precautions appendix 4.1 precautions about the cpu --------------------------------------------------------------------- appendix 4-2 appendix 4.2 precautions about the address space ------------------------------------------------------- appendix 4-3 appendix 4.3 precautions about eit --------------------------------------------------------------------------- appendix 4- 3 appendix 4.4 precautions to be observed when programming internal flash memory --------- appendix 4-3 appendix 4.5 precautions to be observed after exiting reset ------------------------------------------- appendix 4-4 appendix 4.6 precautions about input/output ports -------------------------------------------------------- appendix 4-4 appendix 4.7 precautions about the dmac ------------------------------------------------------------------ appendix 4-5 appendix 4.8 precautions about the multijunction timers ------------------------------------------------ appendix 4-6 appendix 4.8.1 precautions on using top single-shot output mode ---------------------------- appendix 4-6 appendix 4.8.2 precautions on using top delayed single-shot output mode ----------------- appendix 4-8 appendix 4.8.3 precautions on using top continuous output mode ----------------------------- appendix 4-9 appendix 4.8.4 precautions on using tio measure free-run/clear input modes ------------- appendix 4-9 appendix 4.8.5 precautions on using tio pwm outp ut mode -------------------------------------- appendix 4-9 appendix 4.8.6 precautions on using tio single-shot output mode ------------------------------ appendix 4-9 appendix 4.8.7 precautions on using tio delayed single-shot output mode ------------------ appendix 4-10 appendix 4.8.8 precautions on using tio continuous output mode ------------------------------ appendix 4-10 appendix 4.8.9 precautions on using tms measure input ------------------------------------------- appendix 4-10 appendix 4.8.10 precautions on using tml measure input ------------------------------------------ appendix 4-11 appendix 4.9 precautions about the a-d converters ------------------------------------------------------ appendix 4-12 appendix 4.10 precautions about serial i/o ------------------------------------------------------------------- appendix 4-15 appendix 4.10.1 precautions on using csio mode ----------------------------------------------------- appendix 4-15 appendix 4.10.2 precautions on using uart mode ---------------------------------------------------- appendix 4-16 appendix 4.11 precautions about can module --------------------------------------------------------------- appendix 4-17 appendix 4.12 precautions about ram backup mode ------------------------------------------------------ appendix 4-18 appendix 4.13 precautions about jtag ------------------------------------------------------------------------ appendix 4-19 appendix 4.13.1 notes on board design when connecting jtag ----------------------------------- appendix 4-19 appendix 4.13.2 processing pins when not using jtag ---------------------------------------------- appendix 4-20 appendix 4.14 precautions about noise ------------------------------------------------------------------------ appendix 4-21 appendix 4.14.1 reduction of wiring length ------------------------------------------------------------- appendix 4-21 appendix 4.14.2 inserting a bypass capacitor between vss and vcc lines ------------------- appendix 4-23 appendix 4.14.3 processing analog input pin wiring -------------------------------------------------- appendix 4-23 appendix 4.14.4 consideration about the oscillator ----------------------------------------------------- appendix 4-24 appendix 4.14.5 processing input/output ports --------------------------------------------------------- appendix 4-28 chapter 1 overview 1.1 outline of the 32176 group 1.2 block diagram 1.3 pin functions 1.4 pin assignments 1-2 1 overview 32176 group user?s manual (rev.1.01) 1.1 outline of the 32176 group 1.1.1 m32r family cpu core (1) based on a risc architecture ? the 32176 is a 32-bit risc single-chip microcomputer which is built around the m32r family cpu core (hereinafter referred to as the m32r) and incorporates flash memory, ram and various other peripheral functions-all integrated into a single chip. ? the m32r is based on a risc architecture. memory is accessed using load/store instructions, and various arithmetic operations are executed using register-to-register operation instructions. the m32r internally contains sixteen 32-bit general-purpose registers and has 83 instructions. ? the m32r supports compound instructions such as load & address update and store & address update, in addition to ordinary load and store instructions. these instructions help to speed up data transfers. (2) five-stage pipelined processing ? the m32r supports five-stage pipelined instruction processing consisting of instruction fetch, de- code, execute, memory access and write back. not just load/store instructions and register-to-reg- ister operation instructions, compound instructions such as load & address update and store & address update are executed in one cpuclk period (which is equivalent to 25 ns when f(cpuclk) = 40 mhz). ? although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation instruction will be executed before that instruc- tion. using such a facility, which is known as the ?out-of-order-completion? mechanism, the m32r is able to control instruction execution without wasting clock cycles. (3) compact instruction code ? the m32r supports two instruction formats: one 16 bits long, and one 32 bits long. use of the 16-bit instruction format especially helps to suppress the code size of a program. ? moreover, the availability of 32-bit instructions makes programming easier and provides higher per- formance at the same clock speed than in architectures where the address space is segmented. for example, some 32-bit instructions allow control to jump to an address 32 mbytes forward or backward from the currently executed address in one instruction, making programming easy. 1.1.2 built-in multiplier/accumulator (1) built-in high-speed multiplier ? the m32r contains a 32 bits 16 bits high-speed multiplier which enables the m32r to execute a 32 bits 32 bits integral multiplication instruction in three cpuclk periods. (2) dsp-comparable multiply-accumulate instructions ? the m32r supports the following four types of multiply-accumulate instructions (or multiplication instruc- tions) which each can be executed in one cpuclk period using a 56-bit accumulator. (1) 16 high-order bits of register 16 high-order bits of register (2) 16 low-order bits of register 16 low-order bits of register (3) whole 32 bits of register 16 high-order bits of register (4) whole 32 bits of register 16 low-order bits of register ? the m32r has some special instructions to round the value stored in the accumulator to 16 or 32 bits or shift the accumulator value before storing in a register to have its digits adjusted. because these instructions are also executed in one cpuclk period, when used in combination with high-speed data transfer instructions such as load & address update or store & address update, they enable the m32r to exhibit data processing capability comparable to that of a dsp. 1.1 outline of the 32176 group 1 1-3 overview 32176 group user?s manual (rev.1.01) 1.1 outline of the 32176 group 1.1.3 built-in flash memory and ram ? the 32176 contains a ram that can be accessed with zero wait state, allowing to design a high-speed embedded system. ? the internal flash memory can be written to while mounted on a printed circuit board (on-board writ- ing). use of flash memory facilitates development work, because the chip used at the development stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board. ? the internal flash memory has a virtual flash emulation function, allowing the internal ram to be virtually mapped into part of the internal flash memory. when combined with the internal real-time debugger (rtd), this function makes the rom table data tuning easy. ? the internal ram can be accessed for reading or rewriting data from an external device indepen- dently of the m32r by using the real-time debugger. the external device is communicated using the real-time debugger?s exclusive clock-synchronized serial i/o. 1.1.4 built-in clock frequency multiplier ? the 32176 contains a clock frequency multiplier, which is schematically shown in figure 1.1.1 below. xin pin (8mhz-10mhz) bclk (peripheral clock) (16mhz-20mhz) cpuclk (cpu clock) (32mhz-40mhz) x4 1/2 pll figure 1.1.1 conceptual diagram of the clock frequency multiplier table 1.1.1 clock functional block features cpuclk ? cpu clock: defined as f(cpuclk) when it indicates the operating clock frequency for the m32r core, internal flash memory and internal ram. bclk ? peripheral clock: defined as f(bclk) when it indicates the operating clock frequency for the internal peripheral i/o and external data bus. clock output (bclk pin output) ? a clock with the same frequency as f(bclk) is output from this pin. 1-4 1 overview 32176 group user?s manual (rev.1.01) 1.1 outline of the 32176 group 1.1.5 powerful built-in peripheral functions (1) multijunction timer (mjt) (2) 10-channel dmac (3) 16-channel a-d converter (adc) (4) 4-channel high-speed serial i/o (sio) (5) real-time debugger (rtd) (6) 8-level interrupt controller (icu) (7) three operation modes (8) wait controller (9) 2-channel full-can (10) m32r family?s common debug function (scalable debug interface or sdi) 1.1.6 product list of the 32176 group table 1.1.2 product list type name rom size ram size package type cpuclk bclk operating ambient (max frequency) (max frequency) temperature M32176F2VFP 256 kbytes 24 kbytes 144-pin lqfp 32 mhz 16 mhz ?40c to 125c m32176f3vfp 384 kbytes 24 kbytes 144-pin lqfp 32 mhz 16 mhz ?40c to 125c m32176f4vfp 512 kbytes 24 kbytes 144-pin lqfp 32 mhz 16 mhz ?40c to 125c m32176f2tfp 256 kbytes 24 kbytes 144-pin lqfp 40 mhz 20 mhz ?40c to 85c m32176f3tfp 384 kbytes 24 kbytes 144-pin lqfp 40 mhz 20 mhz ?40c to 85c m32176f4tfp 512 kbytes 24 kbytes 144-pin lqfp 40 mhz 20 mhz ?40c to 85c 1 1-5 overview 32176 group user?s manual (rev.1.01) 1.2 block diagram 1.2 block diagram figure 1.2.1 shows a block diagram of the 32176. the features of each block are described in table 1.2.1. figure 1.2.1 block diagram of the 32176 pll clock generator internal bus interface address data internal ram (24 kbytes) internal flash memory (m32176f4: 512 kbytes) (m32176f3: 384 kbytes) (m32176f2: 256 kbytes) m32r core multiplier/accumulator (32 bits 16 bits + 56 bits) dmac (10 channels) multijunction timer (37 channels) serial i/o (4 channels) a-d converter (10-bit converter, 16 channels) wait controller interrupt controller (23 sources, 8 levels) real-time debugger (rtd) external bus interface internal 32-bit bus 96 input/output ports full can (2 channels) internal 16-bit bus internal power supply generator (vdc) 1-6 1 overview 32176 group user?s manual (rev.1.01) 1.2 block diagram table 1.2.1 features of the 32176 (1/2) functional block features m32r cpu core ? implementation: five-stage pipelined instruction processing ? internal 32-bit structure of the core ? register configuration general-purpose registers: 32 bits 16 registers control registers: 32 bits 5 registers ? instruction set 16 and 32-bit instruction formats 83 instructions and six addressing modes ? internal multiplier/accumulator (32 bits 16 bits + 56 bits) ram ? capacity: 24 kbytes ? zero-wait access ? the internal ram can be accessed for reading or rewriting data from the outside independently of the m32r by using the real-time debugger, without ever causing the cpu performance to decrease. flash memory ? capacity: m32176f2: 256 kbytes, m32176f3: 384 kbytes, m32176f4: 512 kbytes ? zero-wait access ? durability: standard product : 100 times 10000 (10k) times rewritable : 4-kbyte block (note 2) : 10,000 (10k) times -product (note 1) : other blocks : 1,000 (1k) times bus specification ? fundamental bus cycle : 25 ns (when f(cpuclk = 40 mhz) ? logical address space : 4 gbytes linear ? internal bus specification : internal 32-bit data bus (for cpu <-> internal flash memory and ram access) : internal 16-bit data bus (for internal peripheral i/o access) ? external area: maximum 2 mbytes (during processor mode) ? external extention area: maximum 2 mbytes ? external data address bus: 19-bit address ? external data bus: 16-bit data bus ? shortest external bus access: 2 bclk periods during read, 2 bclk periods during write dmac ? number of channels: 10 ? transfers between internal peripheral i/o?s or internal ram?s or between internal peripheral i/o and internal ram are supported. ? capable of advanced dma transfers when used in combination with internal peripheral i/o ? transfer request: software or internal peripheral i/o (a-d converter, mjt, serial i/o or can) ? dma channels can be cascaded. (dma transfer on a channel can be started by completion of a transfer on another channel.) ? interrupt request: dma transfer counter register underflow multijunction timer (mjt) ? 37-channel multi-functional timer 16-bit output related timer 11 channels, 16-bit input/output related timer 10 channels, 16-bit input related timer 8 channels, 32-bit input related timer 8 channels ? flexible timer configuration is possible by interconnecting these timer channels. ? interrupt request: counter underflow or overflow and rising or falling or both edges or high or low level from the tin pin (these can be used as external interrupt inputs irrespective of timer operation.) ? dma transfer request: counter underflow or overflow and rising or falling or both edges or high or low level from the tin pin (these can be used as external dma transfer request inputs irrespective of timer operation.) note 1: the 10000 (10k) times rewritable product is offered as an optional item. for details about it, please contact your nearest office of renesas or its distributor. note 2: block 1: h?0000 2000 to h?0000 2ffff block 2: h?0000 3000 to h?0000 3ffff 1 1-7 overview 32176 group user?s manual (rev.1.01) table 1.2.1 features of the 32176 (2/2) 1.2 block diagram functional block features a-d converter (adc) ? 16 channels: 10-bit resolution a-d converter ? conversion modes: ordinary conversion modes plus comparator mode ? operation modes: single conversion mode and n-channel scan mode (n = 1?16) ? sample-and-hold function: sample-and-hold function can be enabled or disabled as necessary. ? a-d disconnection detection assist function: influences of the analog input voltage leakage from any preceding channel during scan mode operation are suppressed. ? an inflow current bypass circuit is built-in. ? can generate an interrupt or start dma transfer upon completion of a-d conversion. ? either 8 or 10-bit conversion results can be read out. ? interrupt request: completion of a-d conversion ? dma transfer request: completion of a-d conversion serial i/o (sio) ? 4-channel serial i/o ? can be chosen to be clock-synchronized serial i/o or uart. ? data can be transferred at high speed (2 mbits per second during clock-synchronized mode or 156 kbits per second during uart mode when f(bclk) = 20 mhz). ? interrupt request: reception completed, receive error, transmit buffer empty or transmission completed ? dma transfer request: reception completed or transmit buffer empty can ? 16 message slots 2 blocks ? compliant with can specification 2.0b active. ? interrupt request: transmission completed, reception completed, bus error, error-passive, bus-off or single shot ? dma transfer request: transmission failed, transmission completed or reception completed real-time debugger ? internal ram can be rewritten or monitored independently of the cpu by entering a command (rtd) from the outside. ? comes with exclusive clock-synchronized serial ports. ? interrupt request: rtd interrupt command input interrupt controller (icu) ? controls interrupt requests from the internal peripheral i/o. ? supports 8-level interrupt priority including an interrupt disabled state. ? external interrupt: 11 sources (sbi#, tin0,tin3, tin16-tin23) ? tin pin input sensing: rising, falling or both edges or high or low level wait controller ? controls wait states for access to the external extention area. ? insertion of 1-4 wait states by setting up in software + wait state extension by entering wait# signal pll ? a multiply-by-4 clock generating circuit clock ? maximum external input clock frequency (xin) is 10.0 mhz. (note 1) ? cpuclk: operating clock for the m32r-cpu core, internal flash memory and internal ram the maximum cpu clock is 40 mhz (when f(xin) = 10 mhz). ? bclk: operating clock for the internal peripheral i/o and external data bus the maximum peripheral clock is 20 mhz (peripheral module access when f(xin) = 10 mhz). ? clock output (bclk pin output): a clock with the same frequency as bclk is output from this pin. jtag ? boundary scan function vdc ? internal power supply generating circuit: generates the internal power supply (2.5 v) from an external single power supply (5 or 3.3 v). ports ? input/output pins: 96 pins ? the port input threshold can be set in a program to one of three levels individually for each port group (with or without schmitt circuit, selectable). note 1: maximum external input clock frequency (xin) for the M32176F2VFP, m32176f3vfp and m32176f4vfp is 8.0 mhz. 1-8 1 overview 32176 group user?s manual (rev.1.01) 1.3 pin functions figure 1.3.1 pin function diagram 1.3 pin functions figure 1.3.1 shows the 32176?s pin function diagram. pin functions are described in table 1.3.1. xin reset# 32176 group excvdd vss p20/a23-p27/a30 p30/a15-p37/a22 p46/a13, p47/a14 p225/a12 address bus 19 p00/db0-p07/db7 p10/db8-p17/db15 data bus 16 p72/hreq# p73/hack# bus control p71/wait# p43/rd# p44/cs0# p45/cs1# p41/blw#/ble# p42/bhw#/bhe# port 2 port 3 port 4 port 22 port 0 port 1 port 7 port 4 xout excosc-vcc osc-vss mod0 mod2 (note 1) mod1 p150/tin0, p153/tin3 p130/tin16-p137/tin23 10 port 15 port 13 p124/tclk0-p127/tclk3 4 multi- junction timer 21 p93/to16-p97/to20 p100/to8-p107/to15 p110/to0-p117/to7 port 12 port 11 port 10 port 9 p74/rtdtxd/txd3 p75/rtdrxd/rxd3 p76/rtdack/ctx1 p77/rtdclk/crx1 real time debugger port 7 p70/bclk/wr# port 7 p82/txd0 p83/rxd0 p84/sclki 0/sclko 0 p85/txd1 p86/rxd1 p87/sclki 1/sclko 1 serial i/o can1 serial i/o port 8 avcc0 p61-p63 port 6 vref0 vdde n.c. (note 2) fp excvcc vcce p174/txd2 p175/rxd2 port 17 16 ad0in0-ad0in15 p220/ctx0 p221/crx0 can0 jtms jtck jtrst jtdo jtag jtdi port 22 sbi# avss0 3 4 2 5 clock reset mode a-d converter interrupt controller note 1: mod2 must be connected to the ground. note 2: n.c. indicates non-connected pin. connect the pin to the power supply, ground, or the like that has no voltage change. note: the pin (signal) with "#" at the end of the pin name (signal name) indicates it is a low active pin (signal). 1 1-9 overview 32176 group user?s manual (rev.1.01) 1.3 pin functions table 1.3.1 description of pin functions (1/4) type pin name signal name input/output description power supply vcce main power supply ? power supply for the device (5.0 v 0.5 v or 3.3 v 0.3 v). excvcc internal power supply ? this pin connects an external capacitor. vdde ram power supply ? backup power supply for the internal ram (5.0 v 0.5 v or 3.3 v 0.3 v). excvdd internal power ? this pin connects an external capacitor for the internal power supply of ram supply of the internal ram. vss ground ? connect all vss pins to ground (gnd). clock xin, clock input input these are clock input/output pins. a pll-based 4 frequency xout clock output output multiplier is included, which accepts as input a clock whose frequency is 1/4 of the internal cpu clock frequency. (xin input is 10 mhz when f(cpuclk) = 40 mhz.) bclk system clock output this pin outputs a clock whose frequency is twice that of the external input clock (xin). (bclk output is 20 mhz when f(cpuclk) = 40 mhz.) use this clock to synchronize the operation of external devices. excosc clock power supply ? this pin connects an external capacitor for the oscillator circuit. -vcc osc-vss clock ground ? connect osc-vss to ground. reset reset# reset input reset input pin for the internal circuit. mode mod0- mode input set the microcomputer?s operation mode. mod2 mod0 mod1 mod2 mode l l l single-chip mode l h l external extension mode h l l processor mode h h l (settings inhibited) (note 1) x x h (settings inhibited) x: don?t care flash fp flash protect input this special pin protects the flash memory against rewrites in hardware. address bus a12?a30 address bus output to allow two areas of up to 1 mb memory space to be connected external to the chip, the device has 19 address lines (a12?a30). a31 is not output. note 1: boot mode requires that the fp pin should be at the high level. for details about boot mode, see chapter 6, ?internal memory.? 1-10 1 overview 32176 group user?s manual (rev.1.01) 1.3 pin functions table 1.3.1 description of pin functions (2/4) type pin name signal name input/output description data bus db0?db15 data bus input/output this 16-bit data bus is used to connect external devices. when writing in byte units during a write cycle, the output data at the invalid byte position is undefined. during a read cycle, data on the entire 16-bit bus is always read in. however, only the data at the valid byte position is transferred into the internal circuit. bus control cs0#,cs1# chip select output these are chip select signals for external devices. rd# read output this signal is output when reading an external device. wr# write output this signal is output when writing to an external device. bhw#,blw# byte high write/ output when writing to an external device, this signal indicates the byte low write valid byte position to which data is transferred. bhw# and blw# correspond to the upper address side (bits 0?7 are valid) and the lower address side (bits 8?15 are valid), respectively. bhe# byte high enable output during an external device access, this signal indicates that the high-order data (bits 0?7) is valid. ble# byte low enable output during an external device access, this signal indicates that the low-order data (bits 8?15) is valid. wait# wait input when accessing an external device, a low-level input on wait# pin extends the wait cycle. hreq# hold request input this input is used by an external device to request control of the external bus. a low-level input on hreq# pin places the cpu in a hold state. hack# hold acknowledge output this signal notifies that the cpu has entered a hold state and relinquished control of the external bus. multijunction tin0, tin3, timer input input input pins for the multijunction timer. timer tin16?tin23 to0?to20 timer output output output pins for the multijunction timer. tclk0 timer clock input clock input pins for the multijunction timer. ?tclk3 a-d converter avcc0 analog power supply ? avcc0 is the power supply for the a-d0 c onverter. connect avcc0 to the power supply rail. avss0 analog ground ? avss0 is the analog ground for the a-d0 converter. connect avss0 to ground. ad0in0 analog input input 16-channel analog input pins for the a-d0 converter. ?ad0in15 vref0 reference voltage input vref0 is the reference voltage input pin for the a-d0 input converter. interrupt sbi# system break input this is the system break interrupt (sbi) input pin for the controller interrupt interrupt controller. 1 1-11 overview 32176 group user?s manual (rev.1.01) 1.3 pin functions table 1.3.1 description of pin functions (3/4) type pin name signal name input/output description serial i/o sclki0/ uart transmit/receive input/output when channel 0 is in uart mode: sclko0 clock output or csio this pin outputs a clock derived from brg output by transmit/receive clock dividing it by 2. input/output when channel 0 is in csio mode: this pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. sclki1/ uart transmit/receive input/output when channel 1 is in uart mode: sclko1 clock output or csio this pin outputs a clock derived from brg output by transmit/receive clock dividing it by 2. input/output when channel 1 is in csio mode: this pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. txd0 transmit data output transmit data output pin for serial i/o channel 0. rxd0 received data input received data input pin for serial i/o channel 0. txd1 transmit data output transmit data output pin for serial i/o channel 1. rxd1 received data input received data input pin for serial i/o channel 1. txd2 transmit data output transmit data output pin for serial i/o channel 2. rxd2 received data input received data input pin for serial i/o channel 2. txd3 transmit data output transmit data output pin for serial i/o channel 3. rxd3 received data input received data input pin for serial i/o channel 3. real-time rtdtxd transmit data output serial data output pin for the real-time debugger. debugger rtdrxd received data input serial data input pin for the real-time debugger. (rtd) rtdclk clock input input serial data transmit/receive clock input pin for the real-time debugger. rtdack acknowledge output a low-level pulse is output from this pin synchronously with the start clock for the real-time debugger?s serial data output word. the low-level pulse width indicates the type of command/ data received by the real-time debugger. can ctx0, ctx1 data output output this pin outputs data from the can module. crx0, crx1 data input input this pin accepts as input the data for the can module. jtag jtms test mode input test mode select input to control the state transition of the test circuit. jtck clock input clock input for the debug module and test circuit. jtrst test reset input test reset input to initialize the test circuit asynchronously with device operation. jtdi serial input input this pin accepts as input the test instruction code or test data that is serially received. jtdo serial output output this pin outputs the test instruction code or test data serially. 1-12 1 overview 32176 group user?s manual (rev.1.01) 1.3 pin functions table 1.3.1 description of pin functions (4/4) type pin name signal name input/output description input/output p00?p07 input/output port 0 input/output programmable input/output port. ports p10?p17 input/output port 1 (note 1) p20?p27 input/output port 2 p30?p37 input/output port 3 p41?p47 input/output port 4 p61?p63 input/output port 6 p70?p77 input/output port 7 p82?p87 input/output port 8 p93?p97 input/output port 9 p100?p107 input/output port 10 p110?p117 input/output port 11 p124?p127 input/output port 12 p130?p137 input/output port 13 p150, p153 input/output port 15 p174, p175 input/output port 17 p220, p225, input/output port 22 p221(note 1) note 1: ? input/output port 5 is reserved for future use. also, input/output ports 14, 16 and 18-21 are nonexistent. note 2: ? p221 is input-only port. 1 1-13 overview 32176 group user?s manual (rev.1.01) 1.4 pin assignments 1.4 pin assignments figure 1.4.1 shows the 32176?s pin assignment diagram. a pin assignment table is shown in table 1.4.1. figure 1.4.1 pin assignment diagram (top view) 44 43 37 38 39 40 41 42 60 59 51 52 53 54 55 56 45 46 47 48 49 50 57 58 63 64 66 67 68 69 70 71 72 65 61 62 89 90 99 98 97 96 95 94 93 92 91 103 102 101 108 10 7 10 6 105 104 73 74 84 75 76 77 78 79 80 81 82 83 85 86 87 88 100 2 4 3 5 6 7 8 9 35 22 23 24 25 26 27 28 29 30 31 32 33 34 11 12 13 14 15 16 17 18 19 20 21 10 1 36 p43/rd# vss excvcc p41/blw#/ble# p153/tin3 p150/tin0 vcce p107/to15 p106/to14 p104/to12 p103/to11 mod2 (note1) p125/tclk1 p124/tclk0 n.c. (note 2) excosc-vcc xout xi n os c-vs s p3 7/a2 2 p3 6/a2 1 p3 3/a1 8 p3 1/a1 6 p3 0/a1 5 p3 5/a2 0 p3 4/ a19 p3 2/a1 7 p27/a3 0 p25/ a28 p2 6/a29 p24/a2 7 p11/ db9 p07/ db7 p0 5/db5 p02/db 2 p0 1/db 1 p00/ db0 p2 3/a26 p2 2/a2 5 p2 0/a2 3 p10/db 8 p06/db6 p0 4/db4 p03/ db3 p21/ a2 4 p44/cs0# p45/cs1# p47/a14 p46/a13 p221/crx0 p14/db12 p15/db13 p16/db14 p17/db15 p82/txd0 p83/rxd0 p174/txd2 p175/rxd2 vss excvcc vref0 avcc0 ad0in7 ad0in6 ad0in5 ad0in4 ad0in3 ad0in2 ad0in1 ad0in0 ad0in15 ad0in14 ad0in13 ad0in12 ad0in11 ad0in10 ad0in9 ad0in8 avss0 p85/txd1 p86/rxd1 rese t# p87/sclki1/sclko1 vss p6 2 fp p9 4/to17 p74/rtdtxd/ txd3 p75/rtdrxd/ rxd3 p76/rtdack/c tx1 p77/rtdclk/c rx1 p61 p6 3 p1 14/ to4 p 115/ to5 p1 16/ to6 p1 17/to7 vc ce mod 1 p1 12/ to2 p1 13 /to3 p7 0/bclk / w r # p71/ wait# p72/ hre q# sbi# mod 0 p93/ to16 p7 3/ hac k# vdde excvdd vs s p127/tclk3 p100/ to8 p1 01/to9 p1 02/ to10 p137/tin23 p136/tin22 p135/tin21 p134/tin20 p105/to13 p1 10 /to0 p1 11/ to1 p97/ to20 p96/to 19 p9 5/to18 p133/tin19 p132/tin18 p131/tin17 p130/tin16 p126/tclk2 jtdi jtdo jtrst jtck jtms p1 2/db 10 p84/sclki0/sclko0 vcce vcce 112 119 116 115 113 111 110 109 120 117 114 124 132 130 129 127 121 137 144 143 142 141 140 139 138 133 136 135 134 123 122 131 128 125 126 118 p220/ctx0 p2 25 /a1 2 p13/db11 vss 32176 group p42/bhw#/bhe# package: 144p6q-a (0.5mm pitch) note 1: mod2 must be connected to the ground. note 2: n.c. indicates non-connected pin. connect the pin to the power supply, ground, or the like that has no voltage change. note: the pin (signal) with "#" at the end of the pin name (signal name) indicates it is a low active pin (signal). 1-14 1 overview 32176 group user?s manual (rev.1.01) 1.4 pin assignments the pins directed for input go to a high-impedance state (hi-z) when reset. the term ?when reset? reffers to the period when input on reset# pin is held low (the device remains reset), as well as when the reset# pin is released back high (the device comes out of reset). table 1.4.1 pin assignments of the 32176 (1/4) port other than port other than port 1 p221/crx0 p221 crx0 - input 3 osc-vss - osc-vss -- 4xin - xin - input 5xout - xo u t - output 6excosc-vcc - excosc- v cc -- 7n.c. ---- function pin no. symbol type - input/output - input/output 2 p225/a12 8 p30/a15 p30 a15 p225 a12 9 p31/a16 p31 a16 - input/output 10 p32/a17 p32 a17 - input/output - input/output - input/output 11 p33/a18 12 p34/a19 p34 a19 p33 a18 13 p35/a20 p35 a20 - input/output 14 p36/a21 p36 a21 - input/output - input/output 15 p37/a22 p37 a22 pin state when reset function type state during reset state upon exiting reset p221 input hi-z hi-z during single-chip mode p225 input hi-z hi-z during external extension and processor modes a12 output hi-z undefined osc-vss --- xin input -- xout output xout xout excosc- v cc --- ---- during single-chip mode p30 input hi-z hi-z during external extension and processor modes a15 output hi-z undefined during single-chip mode p31 input hi-z hi-z during external extension and processor modes a16 output hi-z undefined during single-chip mode p32 input hi-z hi-z during external extension and processor modes a17 output hi-z undefined during single-chip mode p33 input hi-z hi-z during external extension and processor modes a18 output hi-z undefined during single-chip mode p34 input hi-z hi-z during external extension and processor modes a19 output hi-z undefined during single-chip mode p35 input hi-z hi-z during external extension and processor modes a20 output hi-z undefined during single-chip mode p36 input hi-z hi-z during external extension and processor modes a21 output hi-z undefined during single-chip mode p37 input hi-z hi-z during external extension and processor modes a22 output hi-z undefined condition 20 vcce - vcce -- 21 vss - vss -- - input/output 16 p20/a23 p20 a23 17 p21/a24 p21 a24 - input/output 18 p22/a25 p22 a25 - input/output - input/output - input/output 19 p23/a26 22 p24/a27 p24 a27 p23 a26 23 p25/a28 p25 a28 - input/output 24 p26/a29 p26 a29 - input/output - input/output - input/output 25 p27/a30 26 p00/db0 p00 db0 p27 a30 during single-chip mode p20 input hi-z hi-z during external extension and processor modes a23 output hi-z undefined during single-chip mode p21 input hi-z hi-z during external extension and processor modes a24 output hi-z undefined during single-chip mode p22 input hi-z hi-z during external extension and processor modes a25 output hi-z undefined during single-chip mode p23 input hi-z hi-z during external extension and processor modes a26 output hi-z undefined vcce --- vss --- during single-chip mode p24 input hi-z hi-z during external extension and processor modes a27 output hi-z undefined during single-chip mode p25 input hi-z hi-z during external extension and processor modes a28 output hi-z undefined during single-chip mode p26 input hi-z hi-z during external extension and processor modes a29 output hi-z undefined during single-chip mode p27 input hi-z hi-z during external extension and processor modes a30 output hi-z undefined during single-chip mode p00 input hi-z hi-z during external extension and processor modes db0 input/output hi-z hi-z 1 1-15 overview 32176 group user?s manual (rev.1.01) 1.4 pin assignments table 1.4.1 pin assignments of the 32176 (2/4) port other than port other than port - input/output function - input/output - input/output - input/output 30 p04/db4 p04 db4 29 p03/db3 p03 db3 27 p01/db1 p01 db1 28 p02/db2 pin no. - db11 - db9 input/output 37 p13/db11 p13 input/output 36 p12/db10 p12 db10 - input/output 35 p11/db9 p11 - input/output 33 p07/db7 34 p10/db8 p10 db8 p07 db7 - input/output - input/output - input/output 32 p06/db6 p06 db6 31 p05/db5 p05 db5 p02 db2 symbol type pin state when reset function type state during reset state upon exiting reset during single-chip mode p01 input hi-z hi-z during external extension and processor modes db1 input/output hi-z hi-z during single-chip mode p02 input hi-z hi-z during external extension and processor modes db2 input/output hi-z hi-z during single-chip mode p03 input hi-z hi-z during external extension and processor modes db3 input/output hi-z hi-z during single-chip mode p04 input hi-z hi-z during external extension and processor modes db4 input/output hi-z hi-z during single-chip mode p05 input hi-z hi-z during external extension and processor modes db5 input/output hi-z hi-z during single-chip mode p06 input hi-z hi-z during external extension and processor modes db6 input/output hi-z hi-z during single-chip mode p07 input hi-z hi-z during external extension and processor modes db7 input/output hi-z hi-z during single-chip mode p10 input hi-z hi-z during external extension and processor modes db8 input/output hi-z hi-z during single-chip mode p11 input hi-z hi-z during external extension and processor modes db9 input/output hi-z hi-z during single-chip mode p12 input hi-z hi-z during external extension and processor modes db10 input/output hi-z hi-z during single-chip mode p13 input hi-z hi-z during external extension and processor modes db11 input/output hi-z hi-z condition 42 vref0 - vref0 -- 43 avcc0 - avcc0 -- 44 ad0in0 - ad0in0 - input 45 ad0in1 - ad0in1 - input 46 ad0in2 - ad0in2 - input 47 ad0in3 - ad0in3 - input 48 ad0in4 - ad0in4 - input 49 ad0in5 - ad0in5 - input 50 ad0in6 - ad0in6 - input 51 ad0in7 - ad0in7 - input 52 ad0in8 - ad0in8 - input 53 ad0in9 - ad0in9 - input 54 ad0in10 - ad0in10 - input 55 ad0in11 - ad0in11 - input 56 ad0in12 - ad0in12 - input 57 ad0in13 - ad0in13 - input 58 ad0in14 - ad0in14 - input 59 ad0in15 - ad0in15 - input - - db13 input/output 41 p17/db15 p17 db15 input/output 40 p16/db14 p16 db14 - input/output 39 p15/db13 p15 38 p14/db12 p14 db12 - input/output during single-chip mode p14 input hi-z hi-z during external extension and processor modes db12 input/output hi-z hi-z during single-chip mode p15 input hi-z hi-z during external extension and processor modes db13 input/output hi-z hi-z during single-chip mode p16 input hi-z hi-z during external extension and processor modes db14 input/output hi-z hi-z during single-chip mode p17 input hi-z hi-z during external extension and processor modes db15 input/output hi-z hi-z vref0 --- avcc0 --- ad0in0 input hi-z hi-z ad0in1 input hi-z hi-z ad0in2 input hi-z hi-z ad0in3 input hi-z hi-z ad0in4 input hi-z hi-z ad0in5 input hi-z hi-z ad0in6 input hi-z hi-z ad0in7 input hi-z hi-z ad0in8 input hi-z hi-z ad0in9 input hi-z hi-z ad0in10 input hi-z hi-z ad0in11 input hi-z hi-z ad0in12 input hi-z hi-z ad0in13 input hi-z hi-z ad0in14 input hi-z hi-z ad0in15 input hi-z hi-z 1-16 1 overview 32176 group user?s manual (rev.1.01) 1.4 pin assignments table 1.4.1 pin assignments of the 32176 (3/4) port other than port other than port 60 avss0 - avss0 -- 61 excvcc - excvcc -- 62 vss - vss -- 63 p174/txd2 p174 txd2 - input/output 64 p175/rxd2 p175 rxd2 - input/output 65 vcce - vcce - input/output 66 p82/txd0 p82 txd0 - input/output 67 p83/rxd0 p83 rxd0 - input/output 68 p84/sclki0/sclko0 p84 sclki0 sclko0 input/output 69 p85/txd1 p85 txd1 - input/output 70 p86/rxd1 p86 rxd1 - input/output 71 p87/sclki1/sclko1 p87 sclki1 sclko1 input/output 72 vss - vss -- 73 excvdd - excvdd -- 74 p61 p61 -- input/output 75 p62 p62 -- input/output 76 p63 p63 -- input/output 77 sbi# sbi# - input 78 p70/bclk/wr# p70 bclk wr# input/output 79 p71/wait# p71 wait# - input/output 80 p72/hreq# p72 hreq# - input/output 81 p73/hack# p73 hack# - input/output 82 p74/rtdtxd/txd3 p74 rtdtxd txd3 input/output 83 p75/rtdrxd/rxd3 p75 rtdrxd rxd3 input/output 84 p76/rtdack/ctx1 p76 rtdack ctx1 input/output 85 p77/rtdclk/crx1 p77 rtdclk crx1 input/output 86 p93/to16 p93 to16 - input/output 87 p94/to17 p94 to17 - input/output pin no. symbol type function pin state when reset function type state during reset state upon exiting reset avss0 --- excvcc --- vss --- p174 input hi-z hi-z p175 input hi-z hi-z vcce --- p82 input hi-z hi-z p83 input hi-z hi-z p84 input hi-z hi-z p85 input hi-z hi-z p86 input hi-z hi-z p87 input hi-z hi-z vss --- excvdd --- p61 input hi-z hi-z p62 input hi-z hi-z p63 input hi-z hi-z sbi# input hi-z hi-z p70 input hi-z hi-z p71 input hi-z hi-z p72 input hi-z hi-z p73 input hi-z hi-z p74 input hi-z hi-z p75 input hi-z hi-z p76 input hi-z hi-z p77 input hi-z hi-z p93 input hi-z hi-z p94 input hi-z hi-z condition 88 p95/to18 p95 to18 - input/output 89 p96/to19 p96 to19 - input/output 90 p97/to20 p97 to20 - input/output 91 reset# - reset# - input 92 mod0 - mod0 - input 93 mod1 - mod1 - input 94 fp - fp - input 95 vcce - vcce -- 96 vss - vss -- 97 p110/to0 p110 to0 - input/output 98 p111/to1 p111 to1 - input/output 99 p112/to2 p112 to2 - input/output 100 p113/to3 p113 to3 - input/output 101 p114/to4 p114 to4 - input/output 102 p115/to5 p115 to5 - input/output 103 p116/to6 p116 to6 - input/output 104 p117/to7 p117 to7 - input/output 105 p100/to8 p100 to8 - input/output 106 p101/to9 p101 to9 - input/output 107 p102/to10 p102 to10 - input/output 108 vdde - vdde -- 109 jtms (note 1) - jtms - input 110 jtck (note 1) - jtck - input 111 jtrst (note 1) - jtrst - input 112 jtdo (note 1) - jtdo - output 113 jtdi (note 1) - jtdi - input 114 p103/to11 p103 to11 - input/output 115 p104/to12 p104 to12 - input/output 116 p105/to13 p105 to13 - input/output 117 p106/to14 p106 to14 - input/output p95 input hi-z hi-z p96 input hi-z hi-z p97 input hi-z hi-z reset# input hi-z hi-z mod0 input hi-z hi-z mod1 input hi-z hi-z fp input hi-z hi-z vcce --- vss --- p110 input hi-z hi-z p111 input hi-z hi-z p112 input hi-z hi-z p113 input hi-z hi-z p114 input hi-z hi-z p115 input hi-z hi-z p116 input hi-z hi-z p117 input hi-z hi-z p100 input hi-z hi-z p101 input hi-z hi-z p102 input hi-z hi-z vdde --- jtms input hi-z hi-z jtck input hi-z hi-z jtrst input hi-z hi-z jtdo output hi-z hi-z jtdi input hi-z hi-z p103 input hi-z hi-z p104 input hi-z hi-z p105 input hi-z hi-z p106 input hi-z hi-z note 1: the jtck, jtdi, jtdo and jtms pins are reset by input from the jtrst pin, and not reset from the reset# pin. when a low level is applied to the jtrst pin, the jtck, jtdi, jtdo and jtms pins are in the high impedance state. 1 1-17 overview 32176 group user?s manual (rev.1.01) 1.4 pin assignments during single-chip mode p43 input hi-z hi-z during external extension and processor modes rd# output hi-z high level during single-chip mode p44 input hi-z hi-z during external extension and processor modes cs0# output hi-z high level during single-chip mode p45 input hi-z hi-z during external extension and processor modes cs1# output hi-z high level during single-chip mode p46 input hi-z hi-z during external extension and processor modes a13 output hi-z undefined during single-chip mode p47 input hi-z hi-z during external extension and processor modes a14 output hi-z undefined p220 input hi-z hi-z table 1.4.1 pin assignments of the 32176 (4/4) port other than port other than port 118 p107/to15 p107 to15 - input/output 119 p124/tclk0 p124 tclk0 - input/output 120 p125/tclk1 p125 tclk1 - input/output 121 p126/tclk2 p126 tclk2 - input/output 122 p127/tclk3 p127 tclk3 - input/output 123 mod2 - mod2 - - 124 p130/tin16 p130 tin16 - input/output 125 p131/tin17 p131 tin17 - input/output 126 p132/tin18 p132 tin18 - input/output 127 p133/tin19 p133 tin19 - input/output 128 p134/tin20 p134 tin20 - input/output 129 p135/tin21 p135 tin21 - input/output 130 p136/tin22 p136 tin22 - input/output 131 p137/tin23 p137 tin23 - input/output 132 vcce - vcce - - 133 p150/tin0 p150 tin0 - input/output 134 p153/tin3 p153 tin3 - input/output 135 p41/blw#/ble# p41 blw# ble# input/output 136 p42/bhw#/bhe# p42 bhw# bhe# input/output 137 excvcc - excvcc - - 138 vss - vss - - symbol type function pin no. pin state when reset function type state during reset state upon exiting reset p107 input hi-z hi-z p124 input hi-z hi-z p125 input hi-z hi-z p126 input hi-z hi-z p127 input hi-z hi-z mod2--- p130 input hi-z hi-z p131 input hi-z hi-z p132 input hi-z hi-z p133 input hi-z hi-z p134 input hi-z hi-z p135 input hi-z hi-z p136 input hi-z hi-z p137 input hi-z hi-z vcce - - - p150 input hi-z hi-z p153 input hi-z hi-z p41 input hi-z hi-z p42 input hi-z hi-z excvcc - - - vss - - - condition 144 p220/ctx0 p220 ctx0 - input/output 139 p43/rd# p43 rd# - input/output input/output 140 p44/cs0# p44 cs0# - input/output 142 p46/a13 p46 a13 143 p47/a14 p47 a14 - input/output - input/output 141 p45/cs1# p45 cs1# - 1-18 1 overview 32176 group user?s manual (rev.1.01) 1.4 pin assignments this page is blank for reasons of layout. chapter 2 cpu 2.1 cpu registers 2.2 general-purpose registers 2.3 control registers 2.4 accumulator 2.5 program counter 2.6 data formats 2.7 supplementary explanation for lock and unlock instruction execution 2 2-2 32176 group user?s manual (rev.1.01) cpu 2.1 cpu registers 2.1 cpu registers the m32r contains 16 general-purpose registers, five control registers, an accumulator and a program counter. the accumulator is configured with 56 bits, and all other registers are 32 bits wide. 2.2 general-purpose registers the 16 general-purpose registers (r0?r15) are of 32-bit width and are used to retain data, base address, etc. r14 is used as the link register and r15 as the stack pointer. the link register is used to store the return address when executing a subroutine call instruction. the interrupt stack pointer (spi) and the user stack pointer (spu) are alternately represented by r15 depending on the value of the stack mode (sm) bit in the processor status word register (psw). upon exiting the reset state, the value of the general-purpose registers is undefined. figure 2.2.1 general-purpose registers b0 b0 b31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 (link register) r15 (stack pointer) (note 1) note 1: the stack pointer functions as either the spi or the spu depending on the value of the sm bit in the psw. b31 2 2-3 32176 group user?s manual (rev.1.01) cpu 2.3 control registers 2.3 control registers there are 5 control registers which are the processor status word register (psw), the condition bit register (cbr), the interrupt stack pointer (spi), the user stack pointer (spu) and the backup pc (bpc). the dedicated mvtc and mvfc instructions are used for writing and reading these control registers. figure 2.3.1 control registers b0 backup pc bpc cr6 b31 psw cbr spi spu cr0 cr1 cr2 cr3 processor status word register condition bit register interrupt stack pointer user stack pointer crn notes: crn (n = 0-3 and 6) denotes the control register number. the dedicated mvtc and mvfc instructions are used for writing and reading these control registers. 2 2-4 32176 group user?s manual (rev.1.01) cpu 2.3.1 processor status word register: psw (cr0) the processor status word register (psw) indicates the m32r status. it consists of the psw field which is regularly used, and the bpsw field where a copy of the psw field is saved when an eit occurs. the psw field consists of the stack mode (sm) bit, the interrupt enable (ie) bit and the condition (c) bit. the bpsw field consists of the backup stack mode (bsm) bit, the backup interrupt enable (bie) bit and the backup condition (bc) bit. upon exiting the reset state, bsm, bie and bc are undefined. all other bits are "0". 0000 0 00 0000000 7 6 5 4 3 2 1 8 9 1011121314b15 b0 ? ? 00000?00000000 bc sm ie c 23 24 25 26 27 28 29 30 b31 17 18 19 20 21 22 b16 bie bsm bpsw field 0 0 psw field 2 2-5 32176 group user?s manual (rev.1.01) cpu 2.3 control registers 2.3.2 condition bit register: cbr (cr1) the condition bit register (cbr) is derived from the psw register by extracting its condition (c) bit. the value written to the psw register?s c bit is reflected in this register. the register can only be read. (writing to the register with the mvtc instruction is ignored.) upon exiting the reset state, the value of cbr is h?0000 0000. b0 b31 0000000000000000000000000000000 c cbr 2.3.3 interrupt stack pointer: spi (cr2) and user stack pointer: spu (cr3) the interrupt stack pointer (spi) and the user stack pointer (spu) retain the address of the current stack pointer. these registers can be accessed as the general-purpose register r15. r15 switches between repre- senting the spi and spu depending on the value of the stack mode (sm) bit in the psw. upon exiting the reset state, the values of the spi and spu are undefined. b0 b31 spi spi b0 b31 spu spu 2.3.4 backup pc: bpc (cr6) the backup pc (bpc) is used to save the value of the program counter (pc) when an eit occurs. bit 31 is fixed to "0". when an eit occurs, the register sets either the pc value immediately before the eit occurred or the pc value for the next instruction. the bpc value is loaded to the pc when the rte instruction is executed. however, the values of the lower 2 bits of the pc are always "00" when returned. (pc always returns to the word-aligned address.) upon exiting the reset state, the value of the bpc is undefined. b0 b31 0 bpc bpc 2 2-6 32176 group user?s manual (rev.1.01) cpu 2.4 accumulator 2.4 accumulator the accumulator (acc) is a 56-bit register used for dsp function instructions. the accumulator is handled as a 64-bit register when accessed for read or write. when reading data from the accumulator, the value of bit 8 is sign-extended. when writing data to the accumulator, bits 0 to 7 are ignored. the accumulator is also used for the multiply instruction ?mul,? in which case the accumulator value is destroyed by instruction execution. use the mvtachi and mvtaclo instructions for writing to the accumulator. the mvtachi and mvtaclo instructions write data to the high-order 32 bits (bits 0?31) and the low-order 32 bits (bits 32?63), respectively. use the mvfachi, mvfaclo and mvfacmi instructions for reading data from the accumulator. the mvfachi, mvfaclo and mvfacmi instructions read data from the high-order 32 bits (bits 0?31), the low-order 32 bits (bits 32?63) and the middle 32 bits (bits 16?47), respectively. upon exiting the reset state, the value of accumulator is undefined. 15 b0 16 7 8 31 32 47 48 b63 acc (note 1) read range of mvfacmi instruction write and read ranges of mvtaclo and mvfaclo instructions write and read ranges of mvtachi and mvfachi instructions note 1: when read, bits 0 to 7 always show the sign-extended value of the value of bit 8. writing to this bit field is ignored. 2.5 program counter the program counter (pc) is a 32-bit counter that retains the address of the instruction being executed. since the m32r instruction starts with even-numbered addresses, the lsb (bit 31) is always "0". upon exiting the reset state, the value of pc is h?0000 0000. b0 b31 0 pc pc 2 2-7 32176 group user?s manual (rev.1.01) cpu 2.6 data formats 2.6 data formats 2.6.1 data types the data types that can be handled by the m32r instruction set are signed or unsigned 8, 16 and 32-bit integers. the signed integers are represented by 2?s complements. figure 2.6.1 data types signed byte (8-bit) integer unsigned byte (8-bit) integer signed halfword (16-bit) integer unsigned halfword (16-bit) integer signed word (32-bit) integer unsigned word (32-bit) integer b0 b0 b0 b0 b0 b0 b7 b7 b15 b15 b31 b31 s s s s: sign bit 2 2-8 32176 group user?s manual (rev.1.01) cpu 2.6 data formats 2.6.2 data formats (1) data formats in registers the data sizes in the m32r registers are always words (32 bits). when loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (ldb, ldh instructions) or zero-extended (ldub, lduh instructions) to a word (32-bit) quantity before being loaded in the register. when storing data from a register into a memory, the 32-bit data, the 16-bit data on the lsb side and the 8- bit data on the lsb side of the register are stored into memory by the st, sth and stb instructions, respectively. figure 2.6.2 data formats in registers rn b0 b31 2 2-9 32176 group user?s manual (rev.1.01) cpu 2.6 data formats (2) data formats in memory the data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. if an attempt is made to access memory data that overlaps the halfword or word bound- ary, an address exception occurs. figure 2.6.3 data formats in memory address byte halfword word +0 address +1 address +2 address +3 address b0 b31 byte byte byte byte halfword halfword word 7 8 15 16 23 24 b0 15 b0 b31 b31 2 2-10 32176 group user?s manual (rev.1.01) cpu 2.6 data formats (3) endian the diagrams below show a general endian system and the endian adopted for the m32r family micro- computers. bit endian (h'01) byte endian (h'01234567) big endian little endian note: even when bits are arranged in big endian, h'01 is not b'10000000. hh hl lh ll h'01 h'23 h'45 h'67 ll lh hl hh h'67 h'45 h'23 h'01 b'0000001 b0 b7 b'0000001 b7 b0 figure 2.6.4 general endian system little/little ll lh hl hh big/big hh hl lh ll little/big hh hl lh ll endian (bit/byte) data arrangement renesas microcomputer family name 7700 and m16c families m32r family 31?24 7?0 23?16 15?8 0?7 24?31 8?15 16?23 bit number +0 +1 +2 +3 +0 +1 +2 +3 +0 +1 +2 +3 address example: 0x01234567 .byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67 note: the m32r family uses the big endian for both bits and bytes. 7?0 31?24 15?8 23?16 figure 2.6.5 endian adopted for the m32r family 2 2-11 32176 group user?s manual (rev.1.01) cpu 2.6 data formats constant transfer ld24 rdest, #imm24 ldi rdest, #imm16 ldi rdest, #imm8 seth rdest, #imm16 b23 b0 rdest imm24 b31 b0 ld24 rdest, #imm24 b15 b0 rdest imm16 b31 b0 seth rdest, #imm16 00 8 15 00 00 register to register transfer mv rdest, rsrc control register transfer mvfc rdest, crsrc mvtc rsrc, crdest rsrc b31 b0 rdest b31 b0 rsrc b31 b0 crdest b31 b0 mvtc rsrc, crdest mv rdest, rsrc note: the condition bit c changes state when data is written to cr0 (psw) using the mvtc instruction. figure 2.6.6 transfer instructions (4) transfer instructions 2 2-12 32176 group user?s manual (rev.1.01) cpu 2.6 data formats (5) transfer from memory (signed) to registers signed 32 bits ld24 rsrc, #label ld rdest, @rsrc signed 16 bits ld24 rsrc, #label ldh rdest, @rsrc signed 8 bits ld24 rsrc, #label ldb rdest, @rsrc label rdest b31 b0 +0 +1 +2 +3 rdest label 00 00 ff ff determined by msb b31 b0 +0 +1 +2 +3 rdest label 00 00 00 ff ff ff b31 b0 +0 +1 +2 +3 determined by msb memory register 0: positive number 1: negative number 0: positive number 1: negative number unsigned 32 bits ld24 rsrc, #label ld rdest, @rsrc unsigned 16 bits ld24 rsrc, #label ldub rdest, @rsrc unsigned 8 bits ld24 rsrc, #label lduh rdest, @rsrc rdest 00 00 b31 b0 label +0 +1 +2 +3 label +0 +1 +2 +3 rdest b31 b0 label +0 +1 +2 +3 rdest 00 00 00 b31 b0 memory register figure 2.6.7 transfer from memory (signed) to registers (6) transfer from memory (unsigned) to registers figure 2.6.8 transfer from memory (unsigned) to registers 2 2-13 32176 group user?s manual (rev.1.01) cpu 2.6 data formats (7) notes on data transfer when transferring data, be aware that data arrangements in registers and memory are different. word data (32 bits) +0 +1 +2 +3 b0 b31 hh hl lh ll b0 b31 hh hl lh ll halfword data (16 bits) +0 +1 +2 +3 b0 b31 h l b0 b15 h l byte data (8 bits) +0 +1 +2 +3 b0 b31 b0 b7 (r0?r15) (r0?r15) (r0?r15) +0 +1 +2 +3 b0 b31 b8 b15 (r0?r15) +0 +1 +2 +3 b0 b31 b16 b23 (r0?r15) +0 +1 +2 +3 b0 b31 b24 b31 (r0?r15) +0 +1 +2 +3 b0 b31 h l b16 b31 h l (r0?r15) data in registers data in memory figure 2.6.9 difference in data arrangements 2 2-14 32176 group user?s manual (rev.1.01) cpu 2.7 supplementary explanation for lock and unlock instruction execution the lock instruction sets the lock bit, as well as performs an ordinary load operation. the unlock instruction is used to clear the lock bit. the lock bit is located inside the cpu, and cannot directly be accessed for read or write by users. this bit controls granting of bus control requested by devices other than the cpu. ? when lock bit = "0" control of the bus requested by devices other than the cpu is granted ? when lock bit = "1" control of the bus requested by devices other than the cpu is denied control of the bus may be requested by devices other than the cpu in the following two cases: ? when dma transfer is requested by the internal dmac ? when hreq# input is pulled low to request that the cpu be placed in a hold state 2.7 supplementary explanation for bset, bclr, lock and unlock instruction execution chapter 3 address space 3.1 outline of the address space 3.2 operation modes 3.3 internal rom and external extension areas 3.4 internal ram and sfr areas 3.5 eit vector entry 3.6 icu vector table 3.7 notes about address space 3 3-2 address space 3.1 outline of the address space 32176 group user?s manual (rev.1.01) 3.1 outline of the address space the logical addresses of the m32r are always handled in 32 bits, providing a linear address space of up to 4 gbytes. the address space of the m32r consists of the following: (1) user space ? internal rom area ? external extension area ? internal ram area ? sfr (special function register) area (2) system space (not open to the user) (1) user space the 2 gbytes from the address h?0000 0000 to the address h?7fff ffff comprise the user space. located in this space are the internal rom area, an external extension area, the internal ram area and the sfr (special function register) area (in which a set of internal peripheral i/o registers exist). of these, the internal rom and external extension areas are located differently depending on mode settings as will be described later. (2) system space the 2 gbytes from the address h?8000 0000 to the address h?ffff ffff comprise the system space. this space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user. 3 3-3 address space 3.1 outline of the address space 32176 group user?s manual (rev.1.01) h'0000 0000 3 3-4 address space 3.1 outline of the address space 32176 group user?s manual (rev.1.01) h'0000 0000 3 3-5 address space 3.1 outline of the address space 32176 group user?s manual (rev.1.01) figure 3.1.2 address space of the m32176f2 h'0000 0000 3 3-6 address space 32176 group user?s manual (rev.1.01) figure 3.2.1 m32176f4 operation modes and internal rom/external extension areas 3.2 operation modes the microcomputer is placed in one of the following modes depending on how cpu operation mode is set by mod0 and mod1 pins. the operation mode used for rewriting the internal flash memory is described separately in section 6.5, ?programming the internal flash memory.? table 3.2.1 operation mode settings mod0 mod1 mod2 (note 1) operation mode (note 2) vss vss vss single-chip mode vss vcce vss external extension mode vcce vss vss processor mode (fp = vss) vcce vcce vss reserved (use inhibited) -- vcce reserved (use inhibited) note 1: connect vcce and vss to the vcce input power supply and ground, respectively. note 2: for the operation mode used to rewrite the internal flash memory (fp = vcce) which is not shown in the above table, see section 6.5, ?programming the internal flash memory.? the internal rom and external extension areas are located differently depending on how operation mode is set. (all other areas in the address space are located the same way.) the diagram below shows how the internal rom and external extension areas are mapped into the address space in each operation mode. (for flash rewrite mode, see section 6.5, ?programming the internal flash memory.?) 3.2 operation modes h'0000 0000 h'0007 ffff h'0008 0000 h'003f ffff non-cs0 area (internal rom access area) 3 3-7 address space 32176 group user?s manual (rev.1.01) figure 3.2.3 m32176f2 operation modes and internal rom/external extension areas figure 3.2.2 m32176f3 operation modes and internal rom/external extension areas 3.2 operation modes h'0000 0000 h'0005 ffff h'0006 0000 h'003f ffff h'001f ffff h'0020 0000 h'000f ffff h'0010 0000 h'002f ffff h'0030 0000 non-cs0 area 3 3-8 address space 32176 group user?s manual (rev.1.01) 3.3 internal rom and external extension areas the 8-mbyte area in the user space from the address h?0000 0000 to the address h?007f ffff comprise the internal rom and external extension areas. for the address mapping of these areas that differs with each operation mode, see section 3.2, ?operation modes.? 3.3.1 internal rom area the internal rom is allocated to the addresses shown below. located at the beginning of this area is the eit vector entry (and the icu vector table). table 3.3.1 internal rom allocation address type name size allocation address m32176f4 512 kbytes h?0000 0000 to h?0007 ffff m32176f3 384 kbytes h?0000 0000 to h?0005 ffff m32176f2 256 kbytes h?0000 0000 to h?0003 ffff 3.3.2 external extension area the external extension area is only available when external extension or processor mode is selected by operation mode settings. when accessing the external extension area, the control signals necessary to access external devices are output. the cs0# and cs1# signals are output corresponding to the address mapping of the external extension area. the cs0# and cs1# signals are output for the cs0 and cs1 areas, respectively. table 3.3.2 address mapping of the external extension area in each operation mode operation mode address mapping of external extension area single-chip mode none external extension mode h?0010 0000 to h?001f ffff (cs0 area: 1 mbyte) h?0020 0000 to h?002f ffff (cs1 area: 1 mbyte) (note 1) processor mode h?0000 0000 to h?000f ffff (cs0 area: 1 mbyte) (note 2) h?0020 0000 to h?002f ffff (cs1 area: 1 mbyte) (note 2) 3.3 internal rom and external extension areas note 1: during external extension mode, a ghost (1 mbyte) of the cs1 area appears in an area of h'0030 0000 thr ough h'003f ffff. note 2: during processor mode, a ghost (1 mbyte) of the cs0 area appears in an area of h'0010 0000 through h'001f ffff and a ghost (1 mbyte) of the cs1 area appears in an area of h'0030 0000 through h'003f ffff. 3 3-9 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) 3.4 internal ram and sfr areas the 8-mbyte area from the address h?0080 0000 to the address h?00ff ffff comprise the internal ram and sfr (special function register) areas. of these, the space that the user can actually use is a 128-kbyte area from the address h?0080 0000 to the address h?0081 ffff. the other areas here are ghosts in 128-kbyte units. (do not use the ghost area intentionally during programming.) 3.4.1 internal ram area the internal ram area is allocated to the addresses shown below. table 3.4.1 internal ram allocation address type name size allocation address m32176f4 24 kbytes h?0080 4000 to h?0080 9fff m32176f3 24 kbytes h?0080 4000 to h?0080 9fff m32176f2 24 kbytes h?0080 4000 to h?0080 9fff 3.4.2 sfr (special function register) area the addresses h?0080 0000 to h?0080 3ffff comprise the sfr (special function register) area. located in this area are the internal peripheral i/o registers. figure 3.4.1 internal ram and sfr (special function register) areas sfr area (16 kbytes) h'0080 0000 h'0080 3fff h'0080 4000 h'0080 9fff internal ram (24 kbytes) virtual flash emulation areas separated in 8- or 4-kbyte units can be allocated here. for details, see section 6.6. 3 3-10 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) figure 3.4.2 outline mapping of the sfr area h'0080 0000 h'0080 007e h'0080 0180 h'0080 0080 h'0080 00ee h'0080 0100 h'0080 0146 mjt(top) mjt(tio) mjt(tms) h'0080 0200 h'0080 0240 h'0080 0300 h'0080 03c0 h'0080 03e0 h'0080 03fe 0 7 8 15 0 7 8 15 flash control h'0080 07e0 h'0080 07f2 h'0080 023e h'0080 02fe mjt(tml1) h'0080 0fe0 h'0080 0ffe h'0080 0400 dmac h'0080 0478 can1 can0 h'0080 1000 h'0080 11fe h'0080 0700 h'0080 077f h'0080 03be h'0080 03d8 mjt(tml0) h'0080 1400 h'0080 15fe h'0080 3ffe +1 address +0 address interrupt controller (icu) a-d converter serial i/o wait controller mjt (common part) multijunction timer (mjt) input/output port note: ? the real-time debugger (rtd) is an independent module that is operated from the outside, and is transparent to the cpu. multijunction timer (mjt) +1 address +0 address 3 3-11 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) | sfr area register map (1/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 0000 interrupt vector register 5-5 (ivect) h'0080 0002 (use inhibited area) h'0080 0004 interrupt request mask register (use inhibited area) 5-6 (imask) h'0080 0006 sbi control register (use inhibited area) 5-7 (sbicr) (use inhibited area) h'0080 0060 can0 transmit/receive & error interrupt control register (use inhibited area) 5-8 (ican0cr) h'0080 0062 (use inhibited area) h'0080 0064 (use inhibited area) h'0080 0066 (use inhibited area) rtd interrupt control register 5-8 (irtdcr) h'0080 0068 sio2, 3 transmit/receive interrupt control register dma5?9 interrupt control register 5-8 (isio23cr) (idma59cr) h'0080 006a (use inhibited area) h'0080 006c a-d0 conversion interrupt control register sio0 transmit interrupt control register 5-8 (iad0ccr) (isio0txcr) h'0080 006e sio0 receive interrupt control register sio1 transmit interrupt control register 5-8 (isio0rxcr) (isio1txcr) h'0080 0070 sio1 receive interrupt control register dma0?4 interrupt control register 5-8 (isio1rxcr) (idma04cr) h'0080 0072 mjt output interrupt control register 0 mjt output interrupt control register 1 5-8 (imjtocr0) (imjtocr1) h'0080 0074 mjt output interrupt control register 2 mjt output interrupt control register 3 5-8 (imjtocr2) (imjtocr3) h'0080 0076 mjt output interrupt control register 4 mjt output interrupt control register 5 5-8 (imjtocr4) (imjtocr5) h'0080 0078 mjt output interrupt control register 6 mjt output interrupt control register 7 5-8 (imjtocr6) (imjtocr7) h'0080 007a (use inhibited area) mjt input interrupt control register 1 5-8 (imjticr1) h'0080 007c mjt input interrupt control register 2 mjt input interrupt control register 3 5-8 (iimjticr2) (imjticr3) h'0080 007e mjt input interrupt control register 4 can1 transmit/receive & error interrupt control register 5-8 (imjticr4) (ican1cr) h'0080 0080 a-d0 single mode register 0 a-d0 single mode register 1 11-14 (ad0sim0) (ad0sim1) 11-16 h'0080 0082 (use inhibited area) h'0080 0084 a-d0 scan mode register 0 a-d0 scan mode register 1 11-18 (ad0scm0) (ad0scm1) 11-20 h'0080 0086 a -d0 disconnection detection assist function control register a-d0 conversion speed control register 11-23 (ad0ddacr) (ad0cvscr) 11-22 h'0080 0088 a-d0 successive approximation register 11-27 (ad0sar) h'0080 008a a-d0 disconnection detection assist method select register 11-24 (ad0ddasel) h'0080 008c a-d0 comparate data register 11-28 (ad0cmp) h'0080 008e (use inhibited area) h'0080 0090 10-bit a-d0 data register 0 11-29 (ad0dt0) h'0080 0092 10-bit a-d0 data register 1 11-29 (ad0dt1) h'0080 0094 10-bit a-d0 data register 2 11-29 (ad0dt2) h'0080 0096 10-bit a-d0 data register 3 11-29 (ad0dt3) h'0080 0098 10-bit a-d0 data register 4 11-29 (ad0dt4) h'0080 009a 10-bit a-d0 data register 5 11-29 (ad0dt5) 3 3-12 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 009c 10-bit a-d0 data register 6 11-29 (ad0dt6) h'0080 009e 10-bit a-d0 data register 7 11-29 (ad0dt7) h'0080 00a0 10-bit a-d0 data register 8 11-29 (ad0dt8) h'0080 00a2 10-bit a-d0 data register 9 11-29 (ad0dt9) h'0080 00a4 10-bit a-d0 data register 10 11-29 (ad0dt10) h'0080 00a6 10-bit a-d0 data register 11 11-29 (ad0dt11) h'0080 00a8 10-bit a-d0 data register 12 11-29 (ad0dt12) h'0080 00aa 10-bit a-d0 data register 13 11-29 (ad0dt13) h'0080 00ac 10-bit a-d0 data register 14 11-29 (ad0dt14) h'0080 00ae 10-bit a-d0 data register 15 11-29 (ad0dt15) h'0080 00d0 (use inhibited area) 8-bit a-d0 data register 0 11-30 (ad08dt0) h'0080 00d2 (use inhibited area) 8-bit a-d0 data register 1 11-30 (ad08dt1) h'0080 00d4 (use inhibited area) 8-bit a-d0 data register 2 11-30 (ad08dt2) h'0080 00d6 (use inhibited area) 8-bit a-d0 data register 3 11-30 (ad08dt3) h'0080 00d8 (use inhibited area) 8-bit a-d0 data register 4 11-30 (ad08dt4) h'0080 00da (use inhibited area) 8-bit a-d0 data register 5 11-30 (ad08dt5) h'0080 00dc (use inhibited area) 8-bit a-d0 data register 6 11-30 (ad08dt6) h'0080 00de (use inhibited area) 8-bit a-d0 data register 7 11-30 (ad08dt7) h'0080 00e0 (use inhibited area) 8-bit a-d0 data register 8 11-30 (ad08dt8) h'0080 00e2 (use inhibited area) 8-bit a-d0 data register 9 11-30 (ad08dt9) h'0080 00e4 (use inhibited area) 8-bit a-d0 data register 10 11-30 (ad08dt10) h'0080 00e6 (use inhibited area) 8-bit a-d0 data register 11 11-30 (ad08dt11) h'0080 00e8 (use inhibited area) 8-bit a-d0 data register 12 11-30 (ad08dt12) h'0080 00ea (use inhibited area) 8-bit a-d0 data register 13 11-30 (ad08dt13) h'0080 00ec (use inhibited area) 8-bit a-d0 data register 14 11-30 (ad08dt14) h'0080 00ee (use inhibited area) 8-bit a-d0 data register 15 11-30 (ad08dt15) (use inhibited area) h'0080 0100 sio23 interrupt request status register sio03 interrupt request mask register 12-9 (si23stat) (si03mask) 12-10 h'0080 0102 sio03 interrupt request source select register (use inhibited area) 12-11 (si03sel) (use inhibited area) h'0080 0110 sio0 transmit control register sio0 transmit/receive mode register 12-13 (s0tcnt) (s0mod) 12-15 h'0080 0112 sio0 transmit buffer register 12-18 (s0txb) h'0080 0114 sio0 receive buffer register 12-19 (s0rxb) h'0080 0116 sio0 receive control register sio0 baud rate register 12-20 (s0rcnt) (s0baur) 12-23 sfr area register map (2/22) | | 3 3-13 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) | | | | address +0 address +1 address see b0 b7 b8 b15 pages h'0080 0118 sio0 special mode register (use inhibited area) 12-24 (s0smod) (use inhibited area) h'0080 0120 sio1 transmit control register sio1 transmit/receive mode register 12-13 (s1tcnt) (s1mod) 12-15 h'0080 0122 sio1 transmit buffer register 12-18 (s1txb) h'0080 0124 sio1 receive buffer register 12-19 (s1rxb) h'0080 0126 sio1 receive control register sio1 baud rate register 12-20 (s1rcnt) (s1baur) 12-23 h'0080 0128 sio1 special mode register (use inhibited area) 12-24 (s1smod) (use inhibited area) h'0080 0130 sio2 transmit control register sio2 transmit/receive mode register 12-13 (s2tcnt) (s2mod) 12-15 h'0080 0132 sio2 transmit buffer register 12-18 (s2txb) h'0080 0134 sio2 receive buffer register 12-19 (s2rxb) h'0080 0136 sio2 receive control register sio2 baud rate register 12-20 (s2rcnt) (s2baur) 12-23 (use inhibited area) h'0080 0140 sio3 transmit control register sio3 transmit/receive mode register 12-13 (s3tcnt) (s3mod) 12-15 h'0080 0142 sio3 transmit buffer register 12-18 (s3txb) h'0080 0144 sio3 receive buffer register 12-19 (s3rxb) h'0080 0146 sio3 receive control register sio3 baud rate register 12-20 (s3rcnt) (s3baur) 12-23 (use inhibited area) h'0080 0180 wait cycles control register (use inhibited area) 16-4 (wtccr) (use inhibited area) h'0080 0200 (use inhibited area) clock bus & input event bus control register 10-13 (ckiebcr) h'0080 0202 prescaler register 0 prescaler register 1 10-9 (prs0) (prs1) h'0080 0204 prescaler register 2 output event bus control register 10-9 (prs2) (oebcr) 10-14 (use inhibited area) h'0080 0210 tclk input processing control register 10-17 (tclkcr) h'0080 0212 tin input processing control register 0 10-18 (tincr0) h'0080 0214 (use inhibited area) h'0080 0216 (use inhibited area) h'0080 0218 tin input processing control register 3 10-19 (tincr3) h'0080 021a tin input processing control register 4 10-19 (tincr4) h'0080 021c (use inhibited area) h'0080 021e (use inhibited area) h'0080 0220 f/f source select register 0 10-21 (ffs0) h'0080 0222 (use inhibited area) f/f source select register 1 10-22 (ffs1) h'0080 0224 f/f protect register 0 10-23 (ffp0) sfr area register map (3/22) | | 3 3-14 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 0226 f/f data register 0 10-24 (ffd0) h'0080 0228 (use inhibited area) f/f protect register 1 10-23 (ffp1) h'0080 022a (use inhibited area) f/f data register 1 10-24 (ffd1) (use inhibited area) h'0080 0230 top interrupt control register 0 top interrupt control register 1 10-29 (topir0) (topir1) h'0080 0232 top interrupt control register 2 top interrupt control register 3 10-31 (topir2) (topir3) 10-32 h'0080 0234 tio interrupt control register 0 tio interrupt control register 1 10-33 (tioir0) (tioir1) 10-34 h'0080 0236 tio interrupt control register 2 tms interrupt control register 10-35 (tioir2) (tmsir) 10-36 h'0080 0238 tin interrupt control register 0 tin interrupt control register 1 10-37 (tinir0) (tinir1) 10-38 h'0080 023a (use inhibited area) h'0080 023c tin interrupt control register 4 tin interrupt control register 5 10-39 (tinir4) (tinir5) h'0080 023e tin interrupt control register 6 (use inhibited area) 10-41 (tinir6) h'0080 0240 top0 counter 10-53 (top0ct) h'0080 0242 top0 reload register 10-54 (top0rl) h'0080 0244 (use inhibited area) h'0080 0246 top0 correction register 10-55 (top0cc) (use inhibited area) h'0080 0250 top1 counter 10-53 (top1ct) h'0080 0252 top1 reload register 10-54 (top1rl) h'0080 0254 (use inhibited area) h'0080 0256 top1 correction register 10-55 (top1cc) (use inhibited area) h'0080 0260 top2 counter 10-53 (top2ct) h'0080 0262 top2 reload register 10-54 (top2rl) h'0080 0264 (use inhibited area) h'0080 0266 top2 correction register 10-55 (top2cc) (use inhibited area) h'0080 0270 top3 counter 10-53 (top3ct) h'0080 0272 top3 reload register 10-54 (top3rl) h'0080 0274 (use inhibited area) h'0080 0276 top3 correction register 10-55 (top3cc) (use inhibited area) h'0080 0280 top4 counter 10-53 (top4ct) h'0080 0282 top4 reload register 10-54 (top4rl) h'0080 0284 (use inhibited area) sfr area register map (4/22) | | | | | 3 3-15 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 0286 top4 correction register 10-55 (top4cc) (use inhibited area) h'0080 0290 top5 counter 10-53 (top5ct) h'0080 0292 top5 reload register 10-54 (top5rl) h'0080 0294 (use inhibited area) h'0080 0296 top5 correction register 10-55 (top5cc) h'0080 0298 (use inhibited area) h'0080 029a top0?5 control register 0 10-49 (top05cr0) h'0080 029c (use inhibited area) top0?5 control register 1 10-49 (top05cr1) h'0080 029e (use inhibited area) h'0080 02a0 top6 counter 10-53 (top6ct) h'0080 02a2 top6 reload register 10-54 (top6rl) h'0080 02a4 (use inhibited area) h'0080 02a6 top6 correction register 10-55 (top6cc) h'0080 02a8 (use inhibited area) h'0080 02aa top6, 7 control register 10-51 (top67cr) (use inhibited area) h'0080 02b0 top7 counter 10-53 (top7ct) h'0080 02b2 top7 reload register 10-54 (top7rl) h'0080 02b4 (use inhibited area) h'0080 02b6 top7 correction register 10-55 (top7cc) (use inhibited area) h'0080 02c0 top8 counter 10-53 (top8ct) h'0080 02c2 top8 reload register 10-54 (top8rl) h'0080 02c4 (use inhibited area) h'0080 02c6 top8 correction register 10-55 (top8cc) (use inhibited area) h'0080 02d0 top9 counter 10-53 (top9ct) h'0080 02d2 top9 reload register 10-54 (top9rl) h'0080 02d4 (use inhibited area) h'0080 02d6 top9 correction register 10-55 (top9cc) (use inhibited area) h'0080 02e0 top10 counter 10-53 (top10ct) h'0080 02e2 top10 reload register 10-54 (top10rl) h'0080 02e4 (use inhibited area) sfr area register map (5/22) | | | | | 3 3-16 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) address +0 address +1address see b0 b7 b8 b15 pages h'0080 02e6 top10 correction register 10-55 (top10cc) h'0080 02e8 (use inhibited area) h'0080 02ea top8?10 control register 10-52 (top810cr) (use inhibited area) h'0080 02fa top0-10 external enable permit register 10-56 (topeen) h'0080 02fc top0-10 enable protect register 10-56 (toppro) h'0080 02fe top0-10 count enable register 10-57 (topcen) h'0080 0300 tio0 counter 10-87 (tio0ct) h'0080 0302 (use inhibited area) h'0080 0304 tio0 reload 1 register 10-89 (tio0rl1) h'0080 0306 tio0 reload 0/ measure register 10-88 (tio0rl0) (use inhibited area) h'0080 0310 tio1 counter 10-87 (tio1ct) h'0080 0312 (use inhibited area) h'0080 0314 tio1 reload 1 register 10-89 (tio1rl1) h'0080 0316 tio1 reload 0/ measure register 10-88 (tio1rl0) h'0080 0318 (use inhibited area) h'0080 031a tio0?3 control register 0 10-80 (tio03cr0) h'0080 031c (use inhibited area) tio0?3 control register 1 10-81 (tio03cr1) h'0080 031e (use inhibited area) h'0080 0320 tio2 counter 10-87 (tio2ct) h'0080 0322 (use inhibited area) h'0080 0324 tio2 reload 1 register 10-89 (tio2rl1) h'0080 0326 tio2 reload 0/ measure register 10-88 (tio2rl0) (use inhibited area) h'0080 0330 tio3 counter 10-87 (tio3ct) h'0080 0332 (use inhibited area) h'0080 0334 tio3 reload 1 register 10-89 (tio3rl1) h'0080 0336 tio3 reload 0/ measure register 10-88 (tio3rl0) (use inhibited area) h'0080 0340 tio4 counter 10-87 (tio4ct) h'0080 0342 (use inhibited area) h'0080 0344 tio4 reload 1 register 10-89 (tio4rl1) h'0080 0346 tio4 reload 0/ measure register 10-88 (tio4rl0) h'0080 0348 (use inhibited area) sfr area register map (6/22) | | | | 3 3-17 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 034a tio4 control register tio5 control register 10-82 (tio4cr) (tio5cr) 10-84 (use inhibited area) h'0080 0350 tio5 counter 10-87 (tio5ct) h'0080 0352 (use inhibited area) h'0080 0354 tio5 reload 1 register 10-89 (tio5rl1) h'0080 0356 tio5 reload 0/ measure register 10-88 (tio5rl0) (use inhibited area) h'0080 0360 tio6 counter 10-87 (tio6ct) h'0080 0362 (use inhibited area) h'0080 0364 tio6 reload 1 register 10-89 (tio6rl1) h'0080 0366 tio6 reload 0/ measure register 10-88 (tio6rl0) h'0080 0368 (use inhibited area) h'0080 036a tio6 control register tio7 control register 10-85 (tio6cr) (tio7cr) 10-86 (use inhibited area) h'0080 0370 tio7 counter 10-87 (tio7ct) h'0080 0372 (use inhibited area) h'0080 0374 tio7 reload 1 register 10-89 (tio7rl1) h'0080 0376 tio7 reload 0/ measure register 10-88 (tio7rl0) (use inhibited area) h'0080 0380 tio8 counter 10-87 (tio8ct) h'0080 0382 (use inhibited area) h'0080 0384 tio8 reload 1 register 10-89 (tio8rl1) h'0080 0386 tio8 reload 0/ measure register 10-88 (tio8rl0) h'0080 0388 (use inhibited area) h'0080 038a tio8 control register tio9 control register 10-86 (tio8cr) (tio9cr) 10-87 (use inhibited area) h'0080 0390 tio9 counter 10-87 (tio9ct) h'0080 0392 (use inhibited area) h'0080 0394 tio9 reload 1 register 10-89 (tio9rl1) h'0080 0396 tio9 reload 0/ measure register 10-88 (tio9rl0) (use inhibited area) h'0080 03bc tio0-9 enable protect register 10-90 (tiopro) h'0080 03be tio0-9 count enable register 10-91 (tiocen) h'0080 03c0 tms0 counter 10-108 (tms0ct) h'0080 03c2 tms0 measure 3 register 10-108 (tms0mr3) sfr area register map (7/22) | | | | | | 3 3-18 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (8/22) address +0 address +1address see b0 b7 b8 b15 pages h'0080 03c4 tms0 measure 2 register 10-108 (tms0mr2) h'0080 03c6 tms0 measure 1 register 10-108 (tms0mr1) h'0080 03c8 tms0 measure 0 register 10-108 (tms0mr0) h'0080 03ca tms0 control register tms1 control register 10-107 (tms0cr) (tms1cr) (use inhibited area) h'0080 03d0 tms1 counter 10-108 (tms1ct) h'0080 03d2 tms1 measure 3 register 10-108 (tms1mr3) h'0080 03d4 tms1 measure 2 register 10-108 (tms1mr2) h'0080 03d6 tms1 measure 1 register 10-108 (tms1mr1) h'0080 03d8 tms1 measure 0 register 10-108 (tms1mr0) (use inhibited area) h'0080 03e0 tml0 counter (upper) 10-113 (tml0cth) h'0080 03e2 tml0 counter (lower) 10-113 (tml0ctl) (use inhibited area) h'0080 03ea (use inhibited area) tml0 control register 10-112 (tml0cr) (use inhibited area) h'0080 03f0 tml0 measure 3 register (upper) 10-114 (tml0mr3h) h'0080 03f2 tml0 measure 3 register (lower) 10-114 (tml0mr3l) h'0080 03f4 tml0 measure 2 register (upper) 10-114 (tml0mr2h) h'0080 03f6 tml0 measure 2 register (lower) 10-114 (tml0mr2l) h'0080 03f8 tml0 measure 1 register (upper) 10-114 (tml0mr1h) h'0080 03fa tml0 measure 1 register (lower) 10-114 (tml0mr1l) h'0080 03fc tml0 measure 0 register (upper) 10-114 (tml0mr0h) h'0080 03fe tml0 measure 0 register (lower) 10-114 (tml0mr0l) h'0080 0400 dma0?4 interrupt request status register dma0?4 interrupt request mask register 9-18 (dm04itst) (dm04itmk) 9-19 (use inhibited area) h'0080 0408 dma5?9 interrupt request status register dma5?9 interrupt request mask register 9-18 (dm59itst) (dm59itmk) 9-19 (use inhibited area) h'0080 0410 dma0 channel control register dma0 transfer count register 9-6 (dm0cnt) (dm0tct) 9-15 h'0080 0412 dma0 source address register 9-13 (dm0sa) h'0080 0414 dma0 destination address register 9-14 (dm0da) h'0080 0416 (use inhibited area) h'0080 0418 dma5 channel control register dma5 transfer count register 9-8 (dm5cnt) (dm5tct) 9-15 h'0080 041a dma5 source address register 9-13 (dm5sa) h'0080 041c dma5 destination address register 9-14 (dm5da) | | | | | | 3 3-19 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (9/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 041e (use inhibited area) h'0080 0420 dma1 channel control register dma1 transfer count register 9-6 (dm1cnt) (dm1tct) 9-15 h'0080 0422 dma1 source address register 9-13 (dm1sa) h'0080 0424 dma1 destination address register 9-14 (dm1da) h'0080 0426 (use inhibited area) h'0080 0428 dma6 channel control register dma6 transfer count register 9-9 (dm6cnt) (dm6tct) 9-15 h'0080 042a dma6 source address register 9-13 (dm6sa) h'0080 042c dma6 destination address register 9-14 (dm6da) h'0080 042e (use inhibited area) h'0080 0430 dma2 channel control register dma2 transfer count register 9-7 (dm2cnt) (dm2tct) 9-15 h'0080 0432 dma2 source address register 9-13 (dm2sa) h'0080 0434 dma2 destination address register 9-14 (dm2da) h'0080 0436 (use inhibited area) h'0080 0438 dma7 channel control register dma7 transfer count register 9-9 (dm7cnt) (dm7tct) 9-15 h'0080 043a dma7 source address register 9-13 (dm7sa) h'0080 043c dma7 destination address register 9-14 (dm7da) h'0080 043e (use inhibited area) h'0080 0440 dma3 channel control register dma3 transfer count register 9-7 (dm3cnt) (dm3tct) 9-15 h'0080 0442 dma3 source address register 9-13 (dm3sa) h'0080 0444 dma3 destination address register 9-14 (dm3da) h'0080 0446 (use inhibited area) h'0080 0448 dma8 channel control register dma8 transfer count register 9-10 (dm8cnt) (dm8tct) 9-15 h'0080 044a dma8 source address register 9-13 (dm8sa) h'0080 044c dma8 destination address register 9-14 (dm8da) h'0080 044e (use inhibited area) h'0080 0450 dma4 channel control register dma4 transfer count register 9-8 (dm4cnt) (dm4tct) 9-15 h'0080 0452 dma4 source address register 9-13 (dm4sa) h'0080 0454 dma4 destination address register 9-14 (dm4da) h'0080 0456 (use inhibited area) h'0080 0458 dma9 channel control register dma9 transfer count register 9-10 (dm9cnt) (dm9tct) 9-15 h'0080 045a dma9 source address register 9-13 (dm9sa) h'0080 045c dma9 destination address register 9-14 (dm9da) h'0080 045e (use inhibited area) h'0080 0460 dma0 software request generation register 9-12 (dm0sri) h'0080 0462 dma1 software request generation register 9-12 (dm1sri) 3 3-20 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (10/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 0464 dma2 software request generation register 9-12 (dm2sri) h'0080 0466 dma3 software request generation register 9-12 (dm3sri) h'0080 0468 dma4 software request generation register 9-12 (dm4sri) (use inhibited area) h'0080 0470 dma5 software request generation register 9-12 (dm5sri) h'0080 0472 dma6 software request generation register 9-12 (dm6sri) h'0080 0474 dma7 software request generation register 9-12 (dm7sri) h'0080 0476 dma8 software request generation register 9-12 (dm8sri) h'0080 0478 dma9 software request generation register 9-12 (dm9sri) (use inhibited area) h'0080 0700 p0 data register p1 data register 8-7 (p0data) (p1data) h'0080 0702 p2 data register p3 data register 8-7 (p2data) (p3data) h'0080 0704 p4 data register (use inhibited area) 8-7 (p4data) h'0080 0706 p6 data register p7 data register 8-7 (p6data) (p7data) h'0080 0708 p8 data register p9 data register 8-7 (p8data) (p9data) h'0080 070a p10 data register p11 data register 8-7 (p10data) (p11data) h'0080 070c p12 data register p13 data register 8-7 (p12data) (p13data) h'0080 070e (use inhibited area) p15 data register 8-7 (p15data) h'0080 0710 (use inhibited area) p17 data register 8-7 (p17data) h'0080 0712 (use inhibited area) (use inhibited area) h'0080 0714 (use inhibited area) (use inhibited area) h'0080 0716 p22 data register (use inhibited area) 8-7 (p22data) (use inhibited area) h'0080 0720 p0 direction register p1 direction register 8-8 (p0dir) (p1dir) h'0080 0722 p2 direction register p3 direction register 8-8 (p2dir) (p3dir) h'0080 0724 p4 direction register (use inhibited area) 8-8 (p4dir) h'0080 0726 p6 direction register p7 direction register 8-8 (p6dir) (p7dir) h'0080 0728 p8 direction register p9 direction register 8-8 (p8dir) (p9dir) h'0080 072a p10 direction register p11 direction register 8-8 (p10dir) (p11dir) h'0080 072c p12 direction register p13 direction register 8-8 (p12dir) (p13dir) h'0080 072e (use inhibited area) p15 direction register 8-8 (p15dir) h'0080 0730 (use inhibited area) p17 direction register 8-8 (p17dir) h'0080 0732 (use inhibited area) (use inhibited area) h'0080 0734 (use inhibited area) (use inhibited area) | | | 3 3-21 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 0736 p22 direction register (use inhibited area) 8-8 (p22dir) (use inhibited area) h'0080 0744 (use inhibited area) port input special function control register 8-15 (picnt) 18-3 h'0080 0746 (use inhibited area) p7 operation mode register 8-9, 15-4 (p7mod) 18-7 h'0080 0748 p8 operation mode register p9 operation mode register 8-9 (p8mod) (p9mod) 8-10 h'0080 074a p10 operation mode register p11 operation mode register 8-10 (p10mod) (p11mod) 8-11 h'0080 074c p12 operation mode register p13 operation mode register 8-11 (p12mod) (p13mod) 8-12 h'0080 074e (use inhibited area) p15 operation mode register 8-12 (p15mod) h'0080 0750 (use inhibited area) p17 operation mode register 8-13 (p17mod) h'0080 0752 (use inhibited area) (use inhibited area) h'0080 0754 (use inhibited area) (use inhibited area) h'0080 0756 p22 operation mode register (use inhibited area) 8-13 (p22mod) (use inhibited area) h'0080 0760 port group 0, 1 input level setting register port group 3 input level setting register 8-18 (pg01lev) (pg3lev) h'0080 0762 port group 4, 5 input level setting register port group 6, 7 input level setting register 8-18 (pg45lev) (pg67lev) h'0080 0764 port group 8 input level setting register (use inhibited area) 8-18 (pg8lev) h'0080 0766 (use inhibited area) p7 peripheral function select register 8-14 (p7smod) (use inhibited area) h'0080 077a (use inhibited area) rtd write function disable register 14-3 (wrrdis) (use inhibited area) h'0080 077e (use inhibited area) bus mode control register 15-5 (busmodc) (use inhibited area) h'0080 0786 clock control register (use inhibited area) 18-5 (clkcr) (use inhibited area) h'0080 07e0 flash mode register flash status register 6-7 (fmod) (fstat) 6-8 h'0080 07e2 flash control register 1 flash control register 2 6-9 (fcnt1) (fcnt2) 6-10 h'0080 07e4 flash control register 3 flash control register 4 6-11 (fcnt3) (fcnt4) 6-13 h'0080 07e6 (use inhibited area) h'0080 07e8 virtual flash l bank register 0 6-15 (felbank0) h'0080 07ea virtual flash l bank register 1 6-15 (felbank1) (use inhibited area) h'0080 07f0 virtual flash s bank register 0 6-16 (fesbank0) h'0080 07f2 virtual flash s bank register 1 6-16 (fesbank1) (use inhibited area) h'0080 0fe0 tml1 counter (upper) 10-113 (tml1cth) sfr area register map (11/22) | | | | | | | | 3 3-22 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (12/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 0fe2 tml1 counter (lower) 10-113 (tml1ctl) (use inhibited area) h'0080 0fea (use inhibited area) tml1 control register 10-112 (tml1cr) (use inhibited area) h'0080 0ff0 tml1 measure 3 register (upper) 10-115 (tml1mr3h) h'0080 0ff2 tml1 measure 3 register (lower) 10-115 (tml1mr3l) h'0080 0ff4 tml1 measure 2 register (upper) 10-115 (tml1mr2h) h'0080 0ff6 tml1 measure 2 register (lower) 10-115 (tml1mr2l) h'0080 0ff8 tml1 measure 1 register (upper) 10-115 (tml1mr1h) h'0080 0ffa tml1 measure 1 register (lower) 10-115 (tml1mr1l) h'0080 0ffc tml1 measure 0 register (upper) 10-115 (tml1mr0h) h'0080 0ffe tml1 measure 0 register (lower) 10-115 (tml1mr0l) (use inhibited area) h'0080 1000 can0 control register 13-15 (can0cnt) h'0080 1002 can0 status register 13-18 (can0stat) h'0080 1004 can0 extended id register 13-21 (can0extid) h'0080 1006 can0 configuration register 13-22 (can0conf) h'0080 1008 can0 timestamp count register 13-24 (can0tstmp) h'0080 100a can0 receive error count register can0 transmit error count register 13-25 (can0rec) (can0tec) h'0080 100c can0 slot interrupt request status register 13-29 (can0slist) h'0080 100e (use inhibited area) h'0080 1010 can0 slot interrupt request mask register 13-30 (can0slimk) h'0080 1012 (use inhibited area) h'0080 1014 can0 error interrupt request status register can 0 error interrupt request mask register 13-31 (can0erist) (can0erimk) 13-32 h'0080 1016 can0 baud rate prescaler can0 cause of error register 13-26 (can0brp) (can0ef) 13-45 h'0080 1018 can0 mode register can0 dma transfer request select register 13-47 (can0mod) (can0dmarq) 13-48 (use inhibited area) h'0080 1028 can0 global mask register standard id 0 can0 global mask register standard id 1 13-49 (c0gmsks0) (c0gmsks1) h'0080 102a can0 global mask register extended id 0 can0 global mask register extended id 1 13-50 (c0gmske0) (c0gmske1) h'0080 102c can0 global mask register extended id 2 (use inhibited area) 13-51 (c0gmske2) h'0080 102e (use inhibited area) h'0080 1030 can0 local mask register a standard id 0 can0 local mask register a standard id 1 13-49 (c0lmskas0) (c0lmskas1) h'0080 1032 can0 local mask register a extended id 0 can0 local mask register a extended id 1 13-50 (c0lmskae0) (c0lmskae1) h'0080 1034 can0 local mask register a extended id 2 (use inhibited area) 13-51 (c0lmskae2) h'0080 1036 (use inhibited area) | | | | 3 3-23 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (13/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 1038 can0 local mask register b standard id 0 can0 local mask register b standard id 1 13-49 (c0lmskbs0) (c0lmskbs1) h'0080 103a can0 local mask register b extended id 0 can0 local mask register b extended id 1 13-50 (c0lmskbe0) (c0lmskbe1) h'0080 103c can0 local mask register b extended id 2 (use inhibited area) 13-51 (c0lmskbe2) h'0080 103e (use inhibited area) h'0080 1040 can0 single shot mode control register 13-53 (can0ssmode) h'0080 1042 (use inhibited area) h'0080 1044 can0 single-shot interrupt request status register 13-33 (can0ssist) h'0080 1046 (use inhibited area) h'0080 1048 can0 single-shot interrupt request mask register 13-34 (can0ssimk) (use inhibited area) h'0080 1050 can0 message slot 0 control register can0 message slot 1 control register 13-54 (c0msl0cnt) (c0msl1cnt) h'0080 1052 can0 message slot 2 control register can0 message slot 3 control register 13-54 (c0msl2cnt) (c0msl3cnt) h'0080 1054 can0 message slot 4 control register can0 message slot 5 control register 13-54 (c0msl4cnt) (c0msl5cnt) h'0080 1056 can0 message slot 6 control register can0 message slot 7 control register 13-54 (c0msl6cnt) (c0msl7cnt) h'0080 1058 can0 message slot 8 control register can0 message slot 9 control register 13-54 (c0msl8cnt) (c0msl9cnt) h'0080 105a can0 message slot 10 control register can0 message slot 11 control register 13-54 (c0msl10cnt) (c0msl11cnt) h'0080 105c can0 message slot 12 control register can0 message slot 13 control register 13-54 (c0msl12cnt) (c0msl13cnt) h'0080 105e can0 message slot 14 control register can0 message slot 15 control register 13-54 (c0msl14cnt) (c0msl15cnt) (use inhibited area) h'0080 1100 can0 message slot 0 standard id 0 can0 message slot 0 standard id 1 13-58 (c0msl0sid0) (c0msl0sid1) 13-59 h'0080 1102 can0 message slot 0 extended id 0 can0 message slot 0 extended id 1 13-60 (c0msl0eid0) (c0msl0eid1) 13-61 h'0080 1104 can0 message slot 0 extended id 2 can0 message slot 0 data length register 13-62 (c0msl0eid2) (c0msl0dlc) 13-63 h'0080 1106 can0 message slot 0 data 0 can0 message slot 0 data 1 13-64 (c0msl0dt0) (c0msl0dt1) 13-65 h'0080 1108 can0 message slot 0 data 2 can0 message slot 0 data 3 13-66 (c0msl0dt2) (c0msl0dt3) 13-67 h'0080 110a can0 message slot 0 data 4 can0 message slot 0 data 5 13-68 (c0msl0dt4) (c0msl0dt5) 13-69 h'0080 110c can0 message slot 0 data 6 can0 message slot 0 data 7 13-70 (c0msl0dt6) (c0msl0dt7) 13-71 h'0080 110e can0 message slot 0 timestamp 13-72 (c0msl0tsp) h'0080 1110 can0 message slot 1 standard id 0 can0 message slot 1 standard id 1 13-58 (c0msl1sid0) (c0msl1sid1) 13-59 h'0080 1112 can0 message slot 1 extended id 0 can0 message slot 1 extended id 1 13-60 (c0msl1eid0) (c0msl1eid1) 13-61 h'0080 1114 can0 message slot 1 extended id 2 can0 message slot 1 data length register 13-62 (c0msl1eid2) (c0msl1dlc) 13-63 h'0080 1116 can0 message slot 1 data 0 can0 message slot 1 data 1 13-64 (c0msl1dt0) (c0msl1dt1) 13-65 h'0080 1118 can0 message slot 1 data 2 can0 message slot 1 data 3 13-66 (c0msl1dt2) (c0msl1dt3) 13-67 h'0080 111a can0 message slot 1 data 4 can0 message slot 1 data 5 13-68 (c0msl1dt4) (c0msl1dt5) 13-69 h'0080 111c can0 message slot 1 data 6 can0 message slot 1 data 7 13-70 (c0msl1dt6) (c0msl1dt7) 13-71 h'0080 111e can0 message slot 1 timestamp 13-72 (c0msl1tsp) | | 3 3-24 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (14/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 1120 can0 message slot 2 standard id 0 can0 message slot 2 standard id 1 13-58 (c0msl2sid0) (c0msl2sid1) 13-59 h'0080 1122 can0 message slot 2 extended id 0 can0 message slot 2 extended id 1 13-60 (c0msl2eid0) (c0msl2eid1) 13-61 h'0080 1124 can0 message slot 2 extended id 2 can0 message slot 2 data length register 13-62 (c0msl2eid2) (c0msl2dlc) 13-63 h'0080 1126 can0 message slot 2 data 0 can0 message slot 2 data 1 13-64 (c0msl2dt0) (c0msl2dt1) 13-65 h'0080 1128 can0 message slot 2 data 2 can0 message slot 2 data 3 13-66 (c0msl2dt2) (c0msl2dt3) 13-67 h'0080 112a can0 message slot 2 data 4 can0 message slot 2 data 5 13-68 (c0msl2dt4) (c0msl2dt5) 13-69 h'0080 112c can0 message slot 2 data 6 can0 message slot 2 data 7 13-70 (c0msl2dt6) (c0msl2dt7) 13-71 h'0080 112e can0 message slot 2 timestamp 13-72 (c0msl2tsp) h'0080 1130 can0 message slot 3 standard id 0 can0 message slot 3 standard id 1 13-58 (c0msl3sid0) (c0msl3sid1) 13-59 h'0080 1132 can0 message slot 3 extended id 0 can0 message slot 3 extended id 1 13-60 (c0msl3eid0) (c0msl3eid1) 13-61 h'0080 1134 can0 message slot 3 extended id 2 can0 message slot 3 data length register 13-62 (c0msl3eid2) (c0msl3dlc) 13-63 h'0080 1136 can0 message slot 3 data 0 can0 message slot 3 data 1 13-64 (c0msl3dt0) (c0msl3dt1) 13-65 h'0080 1138 can0 message slot 3 data 2 can0 message slot 3 data 3 13-66 (c0msl3dt2) (c0msl3dt3) 13-67 h'0080 113a can0 message slot 3 data 4 can0 message slot 3 data 5 13-68 (c0msl3dt4) (c0msl3dt5) 13-69 h'0080 113c can0 message slot 3 data 6 can0 message slot 3 data 7 13-70 (c0msl3dt6) (c0msl3dt7) 13-71 h'0080 113e can0 message slot 3 timestamp 13-72 (c0msl3tsp) h'0080 1140 can0 message slot 4 standard id 0 can0 message slot 4 standard id 1 13-58 (c0msl4sid0) (c0msl4sid1) 13-59 h'0080 1142 can0 message slot 4 extended id 0 can0 message slot 4 extended id 1 13-60 (c0msl4eid0) (c0msl4eid1) 13-61 h'0080 1144 can0 message slot 4 extended id 2 can0 message slot 4 data length register 13-62 (c0msl4eid2) (c0msl4dlc) 13-63 h'0080 1146 can0 message slot 4 data 0 can0 message slot 4 data 1 13-64 (c0msl4dt0) (c0msl4dt1) 13-65 h'0080 1148 can0 message slot 4 data 2 can0 message slot 4 data 3 13-66 (c0msl4dt2) (c0msl4dt3) 13-67 h'0080 114a can0 message slot 4 data 4 can0 message slot 4 data 5 13-68 (c0msl4dt4) (c0msl4dt5) 13-69 h'0080 114c can0 message slot 4 data 6 can0 message slot 4 data 7 13-70 (c0msl4dt6) (c0msl4dt7) 13-71 h'0080 114e can0 message slot 4 timestamp 13-72 (c0msl4tsp) h'0080 1150 can0 message slot 5 standard id 0 can0 message slot 5 standard id 1 13-58 (c0msl5sid0) (c0msl5sid1) 13-59 h'0080 1152 can0 message slot 5 extended id 0 can0 message slot 5 extended id 1 13-60 (c0msl5eid0) (c0msl5eid1) 13-61 h'0080 1154 can0 message slot 5 extended id 2 can0 message slot 5 data length register 13-62 (c0msl5eid2) (c0msl5dlc) 13-63 h'0080 1156 can0 message slot 5 data 0 can0 message slot 5 data 1 13-64 (c0msl5dt0) (c0msl5dt1) 13-65 h'0080 1158 can0 message slot 5 data 2 can0 message slot 5 data 3 13-66 (c0msl5dt2) (c0msl5dt3) 13-67 h'0080 115a can0 message slot 5 data 4 can0 message slot 5 data 5 13-68 (c0msl5dt4) (c0msl5dt5) 13-69 h'0080 115c can0 message slot 5 data 6 can0 message slot 5 data 7 13-70 (c0msl5dt6) (c0msl5dt7) 13-71 h'0080 115e can0 message slot 5 timestamp 13-72 (c0msl5tsp) 3 3-25 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (15/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 1160 can0 message slot 6 standard id 0 can0 message slot 6 standard id 1 13-58 (c0msl6sid0) (c0msl6sid1) 13-59 h'0080 1162 can0 message slot 6 extended id 0 can0 message slot 6 extended id 1 13-60 (c0msl6eid0) (c0msl6eid1) 13-61 h'0080 1164 can0 message slot 6 extended id 2 can0 message slot 6 data length register 13-62 (c0msl6eid2) (c0msl6dlc) 13-63 h'0080 1166 can0 message slot 6 data 0 can0 message slot 6 data 1 13-64 (c0msl6dt0) (c0msl6dt1) 13-65 h'0080 1168 can0 message slot 6 data 2 can0 message slot 6 data 3 13-66 (c0msl6dt2) (c0msl6dt3) 13-67 h'0080 116a can0 message slot 6 data 4 can0 message slot 6 data 5 13-68 (c0msl6dt4) (c0msl6dt5) 13-69 h'0080 116c can0 message slot 6 data 6 can0 message slot 6 data 7 13-70 (c0msl6dt6) (c0msl6dt7) 13-71 h'0080 116e can0 message slot 6 timestamp 13-72 (c0msl6tsp) h'0080 1170 can0 message slot 7 standard id 0 can0 message slot 7 standard id 1 13-58 (c0msl7sid0) (c0msl7sid1) 13-59 h'0080 1172 can0 message slot 7 extended id 0 can0 message slot 7 extended id 1 13-60 (c0msl7eid0) (c0msl7eid1) 13-61 h'0080 1174 can0 message slot 7 extended id 2 can0 message slot 7 data length register 13-62 (c0msl7eid2) (c0msl7dlc) 13-63 h'0080 1176 can0 message slot 7 data 0 can0 message slot 7 data 1 13-64 (c0msl7dt0) (c0msl7dt1) 13-65 h'0080 1178 can0 message slot 7 data 2 can0 message slot 7 data 3 13-66 (c0msl7dt2) (c0msl7dt3) 13-67 h'0080 117a can0 message slot 7 data 4 can0 message slot 7 data 5 13-68 (c0msl7dt4) (c0msl7dt5) 13-69 h'0080 117c can0 message slot 7 data 6 can0 message slot 7 data 7 13-70 (c0msl7dt6) (c0msl7dt7) 13-71 h'0080 117e can0 message slot 7 timestamp 13-72 (c0msl7tsp) h'0080 1180 can0 message slot 8 standard id 0 can0 message slot 8 standard id 1 13-58 (c0msl8sid0) (c0msl8sid1) 13-59 h'0080 1182 can0 message slot 8 extended id 0 can0 message slot 8 extended id 1 13-60 (c0msl8eid0) (c0msl8eid1) 13-61 h'0080 1184 can0 message slot 8 extended id 2 can0 message slot 8 data length register 13-62 (c0msl8eid2) (c0msl8dlc) 13-63 h'0080 1186 can0 message slot 8 data 0 can0 message slot 8 data 1 13-64 (c0msl8dt0) (c0msl8dt1) 13-65 h'0080 1188 can0 message slot 8 data 2 can0 message slot 8 data 3 13-66 (c0msl8dt2) (c0msl8dt3) 13-67 h'0080 118a can0 message slot 8 data 4 can0 message slot 8 data 5 13-68 (c0msl8dt4) (c0msl8dt5) 13-69 h'0080 118c can0 message slot 8 data 6 can0 message slot 8 data 7 13-70 (c0msl8dt6) (c0msl8dt7) 13-71 h'0080 118e can0 message slot 8 timestamp 13-72 (c0msl8tsp) h'0080 1190 can0 message slot 9 standard id 0 can0 message slot 9 standard id 1 13-58 (c0msl9sid0) (c0msl9sid1) 13-59 h'0080 1192 can0 message slot 9 extended id 0 can0 message slot 9 extended id 1 13-60 (c0msl9eid0) (c0msl9eid1) 13-61 h'0080 1194 can0 message slot 9 extended id 2 can0 message slot 9 data length register 13-62 (c0msl9eid2) (c0msl9dlc) 13-63 h'0080 1196 can0 message slot 9 data 0 can0 message slot 9 data 1 13-64 (c0msl9dt0) (c0msl9dt1) 13-65 h'0080 1198 can0 message slot 9 data 2 can0 message slot 9 data 3 13-66 (c0msl9dt2) (c0msl9dt3) 13-67 h'0080 119a can0 message slot 9 data 4 can0 message slot 9 data 5 13-68 (c0msl9dt4) (c0msl9dt5) 13-69 h'0080 119c can0 message slot 9 data 6 can0 message slot 9 data 7 13-70 (c0msl9dt6) (c0msl9dt7) 13-71 h'0080 119e can0 message slot 9 timestamp 13-72 (c0msl9tsp) 3 3-26 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (16/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 11a0 can0 message slot 10 standard id 0 can0 message slot 10 standard id 1 13-58 (c0msl10sid0) (c0msl10sid1) 13-59 h'0080 11a2 can0 message slot 10 extended id 0 can0 message slot 10 extended id 1 13-60 (c0msl10eid0) (c0msl10eid1) 13-61 h'0080 11a4 can0 message slot 10 extended id 2 can0 message slot 10 data length register 13-62 (c0msl10eid2) (c0msl10dlc) 13-63 h'0080 11a6 can0 message slot 10 data 0 can0 message slot 10 data 1 13-64 (c0msl10dt0) (c0msl10dt1) 13-65 h'0080 11a8 can0 message slot 10 data 2 can0 message slot 10 data 3 13-66 (c0msl10dt2) (c0msl10dt3) 13-67 h'0080 11aa can0 message slot 10 data 4 can0 message slot 10 data 5 13-68 (c0msl10dt4) (c0msl10dt5) 13-69 h'0080 11ac can0 message slot 10 data 6 can0 message slot 10 data 7 13-70 (c0msl10dt6) (c0msl10dt7) 13-71 h'0080 11ae can0 message slot 10 timestamp 13-72 (c0msl10tsp) h'0080 11b0 can0 message slot 11 standard id 0 can0 message slot 11 standard id 1 13-58 (c0msl11sid0) (c0msl11sid1) 13-59 h'0080 11b2 can0 message slot 11 extended id 0 can0 message slot 11 extended id 1 13-60 (c0msl11eid0) (c0msl11eid1) 13-61 h'0080 11b4 can0 message slot 11 extended id 2 can0 message slot 11 data length register 13-62 (c0msl11eid2) (c0msl11dlc) 13-63 h'0080 11b6 can0 message slot 11 data 0 can0 message slot 11 data 1 13-64 (c0msl11dt0) (c0msl11dt1) 13-65 h'0080 11b8 can0 message slot 11 data 2 can0 message slot 11 data 3 13-66 (c0msl11dt2) (c0msl11dt3) 13-67 h'0080 11ba can0 message slot 11 data 4 can0 message slot 11 data 5 13-68 (c0msl11dt4) (c0msl11dt5) 13-69 h'0080 11bc can0 message slot 11 data 6 can0 message slot 11 data 7 13-70 (c0msl11dt6) (c0msl11dt7) 13-71 h'0080 11be can0 message slot 11 timestamp 13-72 (c0msl11tsp) h'0080 11c0 can0 message slot 12 standard id 0 can0 message slot 12 standard id 1 13-58 (c0msl12sid0) (c0msl12sid1) 13-59 h'0080 11c2 can0 message slot 12 extended id 0 can0 message slot 12 extended id 1 13-60 (c0msl12eid0) (c0msl12eid1) 13-61 h'0080 11c4 can0 message slot 12 extended id 2 can0 message slot 12 data length register 13-62 (c0msl12eid2) (c0msl12dlc) 13-63 h'0080 11c6 can0 message slot 12 data 0 can0 message slot 12 data 1 13-64 (c0msl12dt0) (c0msl12dt1) 13-65 h'0080 11c8 can0 message slot 12 data 2 can0 message slot 12 data 3 13-66 (c0msl12dt2) (c0msl12dt3) 13-67 h'0080 11ca can0 message slot 12 data 4 can0 message slot 12 data 5 13-68 (c0msl12dt4) (c0msl12dt5) 13-69 h'0080 11cc can0 message slot 12 data 6 can0 message slot 12 data 7 13-70 (c0msl12dt6) (c0msl12dt7) 13-71 h'0080 11ce can0 message slot 12 timestamp 13-72 (c0msl12tsp) h'0080 11d0 can0 message slot 13 standard id 0 can0 message slot 13 standard id 1 13-58 (c0msl13sid0) (c0msl13sid1) 13-59 h'0080 11d2 can0 message slot 13 extended id 0 can0 message slot 13 extended id 1 13-60 (c0msl13eid0) (c0msl13eid1) 13-61 h'0080 11d4 can0 message slot 13 extended id 2 can0 message slot 13 data length register 13-62 (c0msl13eid2) (c0msl13dlc) 13-63 h'0080 11d6 can0 message slot 13 data 0 can0 message slot 13 data 1 13-64 (c0msl13dt0) (c0msl13dt1) 13-65 h'0080 11d8 can0 message slot 13 data 2 can0 message slot 13 data 3 13-66 (c0msl13dt2) (c0msl13dt3) 13-67 h'0080 11da can0 message slot 13 data 4 can0 message slot 13 data 5 13-68 (c0msl13dt4) (c0msl13dt5) 13-69 h'0080 11dc can0 message slot 13 data 6 can0 message slot 13 data 7 13-70 (c0msl13dt6) (c0msl13dt7) 13-71 h'0080 11de can0 message slot 13 timestamp 13-72 (c0msl13tsp) 3 3-27 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (17/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 11e0 can0 message slot 14 standard id 0 can0 message slot 14 standard id 1 13-58 (c0msl14sid0) (c0msl14sid1) 13-59 h'0080 11e2 can0 message slot 14 extended id 0 can0 message slot 14 extended id 1 13-60 (c0msl14eid0) (c0msl14eid1) 13-61 h'0080 11e4 can0 message slot 14 extended id 2 can0 message slot 14 data length register 13-62 (c0msl14eid2) (c0msl14dlc) 13-63 h'0080 11e6 can0 message slot 14 data 0 can0 message slot 14 data 1 13-64 (c0msl14dt0) (c0msl14dt1) 13-65 h'0080 11e8 can0 message slot 14 data 2 can0 message slot 14 data 3 13-66 (c0msl14dt2) (c0msl14dt3) 13-67 h'0080 11ea can0 message slot 14 data 4 can0 message slot 14 data 5 13-68 (c0msl14dt4) (c0msl14dt5) 13-69 h'0080 11ec can0 message slot 14 data 6 can0 message slot 14 data 7 13-70 (c0msl14dt6) (c0msl14dt7) 13-71 h'0080 11ee can0 message slot 14 timestamp 13-72 (c0msl14tsp) h'0080 11f0 can0 message slot 15 standard id 0 can0 message slot 15 standard id 1 13-58 (c0msl15sid0) (c0msl15sid1) 13-59 h'0080 11f2 can0 message slot 15 extended id 0 can0 message slot 15 extended id 1 13-60 (c0msl15eid0) (c0msl15eid1) 13-61 h'0080 11f4 can0 message slot 15 extended id 2 can0 message slot 15 data length register 13-62 (c0msl15eid2) (c0msl15dlc) 13-63 h'0080 11f6 can0 message slot 15 data 0 can0 message slot 15 data 1 13-64 (c0msl15dt0) (c0msl15dt1) 13-65 h'0080 11f8 can0 message slot 15 data 2 can0 message slot 15 data 3 13-66 (c0msl15dt2) (c0msl15dt3) 13-67 h'0080 11fa can0 message slot 15 data 4 can0 message slot 15 data 5 13-68 (c0msl15dt4) (c0msl15dt5) 13-69 h'0080 11fc can0 message slot 15 data 6 can0 message slot 15 data 7 13-70 (c0msl15dt6) (c0msl15dt7) 13-71 h'0080 11fe can0 message slot 15 timestamp 13-72 (c0msl15tsp) (use inhibited area) h'0080 1400 can1 control register 13-15 (can1cnt) h'0080 1402 can1 status register 13-18 (can1stat) h'0080 1404 can1 extended id register 13-21 (can1extid) h'0080 1406 can1 configuration register 13-22 (can1conf) h'0080 1408 can1 timestamp count register 13-24 (can1tstmp) h'0080 140a can1 receive error count register can1 transmit error count register 13-25 (can1rec) (can1tec) h'0080 140c can1 slot interrupt request status register 13-29 (can1slist) h'0080 140e (use inhibited area) h'0080 1410 can1 slot interrupt request mask register 13-30 (can1slimk) h'0080 1412 (use inhibited area) h'0080 1414 can1 error interrupt request status register can1 e rror interrupt request mask register 13-31 (can1erist) (can1erimk) 13-32 h'0080 1416 can1 baud rate prescaler can1 cause of error register 13-26 (can1brp) (can1ef) 13-45 h'0080 1418 can1 mode register can1 dma transfer request select register 13-47 (can1mod) (can1dmarq) 13-48 (use inhibited area) h'0080 1428 can1 global mask register standard id 0 can1 global mask register standard id 1 13-49 (c1gmsks0) (c1gmsks1) h'0080 142a can1 global mask register extended id 0 can1 global mask register extended id 1 13-50 (c1gmske0) (c1gmske1) h'0080 142c can1 global mask register extended id 2 (use inhibited area) 13-51 (c1gmske2) h'0080 142e (use inhibited area) | | | 3 3-28 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (18/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 1430 can1 local mask register a standard id 0 can1 local mask register a standard id 1 13-49 (c1lmskas0) (c1lmskas1) h'0080 1432 can1 local mask register a extended id 0 can1 local mask register a extended id 1 13-50 (c1lmskae0) (c1lmskae1) h'0080 1434 can1 local mask register a extended id 2 (use inhibited area) 13-51 (c1lmskae2) h'0080 1436 (use inhibited area) h'0080 1438 can1 local mask register b standard id 0 can1 local mask register b standard id 1 13-49 (c1lmskbs0) (c1lmskbs1) h'0080 143a can1 local mask register b extended id 0 can1 local mask register b extended id 1 13-50 (c1lmskbe0) (c1lmskbe1) h'0080 143c can1 local mask register b extended id 2 (use inhibited area) 13-51 (c1lmskbe2) h'0080 143e (use inhibited area) h'0080 1440 can1 single-shot mode control register 13-53 (can1ssmode) h'0080 1442 (use inhibited area) h'0080 1444 can1 single-shot interrupt request status register 13-33 (can1ssist) h'0080 1446 (use inhibited area) h'0080 1448 can1 single-shot interrupt request mask register 13-34 (can1ssimk) (use inhibited area) h'0080 1450 can1 message slot 0 control register can1 message slot 1 control register 13-54 (c1msl0cnt) (c1msl1cnt) h'0080 1452 can1 message slot 2 control register can1 message slot 3 control register 13-54 (c1msl2cnt) (c1msl3cnt) h'0080 1454 can1 message slot 4 control register can1 message slot 5 control register 13-54 (c1msl4cnt) (c1msl5cnt) h'0080 1456 can1 message slot 6 control register can1 message slot 7 control register 13-54 (c1msl6cnt) (c1msl7cnt) h'0080 1458 can1 message slot 8 control register can1 message slot 9 control register 13-54 (c1msl8cnt) (c1msl9cnt) h'0080 145a can1 message slot 10 control register can1 message slot 11 control register 13-54 (c1msl10cnt) (c1msl11cnt) h'0080 145c can1 message slot 12 control register can1 message slot 13 control register 13-54 (c1msl12cnt) (c1msl13cnt) h'0080 145e can1 message slot 14 control register can1 message slot 15 control register 13-54 (c1msl14cnt) (c1msl15cnt) (use inhibited area) h'0080 1500 can1 message slot 0 standard id 0 can1 message slot 0 standard id 1 13-58 (c1msl0sid0) (c1msl0sid1) 13-59 h'0080 1502 can1 message slot 0 extended id 0 can1 message slot 0 extended id 1 13-60 (c1msl0eid0) (c1msl0eid1) 13-61 h'0080 1504 can1 message slot 0 extended id 2 can1 message slot 0 data length register 13-62 (c1msl0eid2) (c1msl0dlc) 13-63 h'0080 1506 can1 message slot 0 data 0 can1 message slot 0 data 1 13-64 (c1msl0dt0) (c1msl0dt1) 13-65 h'0080 1508 can1 message slot 0 data 2 can1 message slot 0 data 3 13-66 (c1msl0dt2) (c1msl0dt3) 13-67 h'0080 150a can1 message slot 0 data 4 can1 message slot 0 data 5 13-68 (c1msl0dt4) (c1msl0dt5) 13-69 h'0080 150c can1 message slot 0 data 6 can1 message slot 0 data 7 13-70 (c1msl0dt6) (c1msl0dt7) 13-71 h'0080 150e can1 message slot 0 timestamp 13-72 (c1msl0tsp) | | 3 3-29 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (19/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 1510 can1 message slot 1 standard id 0 can1 message slot 1 standard id 1 13-58 (c1msl1sid0) (c1msl1sid1) 13-59 h'0080 1512 can1 message slot 1 extended id 0 can1 message slot 1 extended id 1 13-60 (c1msl1eid0) (c1msl1eid1) 13-61 h'0080 1514 can1 message slot 1 extended id 2 can1 message slot 1 data length register 13-62 (c1msl1eid2) (c1msl1dlc) 13-63 h'0080 1516 can1 message slot 1 data 0 can1 message slot 1 data 1 13-64 (c1msl1dt0) (c1msl1dt1) 13-65 h'0080 1518 can1 message slot 1 data 2 can1 message slot 1 data 3 13-66 (c1msl1dt2) (c1msl1dt3) 13-67 h'0080 151a can1 message slot 1 data 4 can1 message slot 1 data 5 13-68 (c1msl1dt4) (c1msl1dt5) 13-69 h'0080 151c can1 message slot 1 data 6 can1 message slot 1 data 7 13-70 (c1msl1dt6) (c1msl1dt7) 13-71 h'0080 151e can1 message slot 1 timestamp 13-72 (c1msl1tsp) h'0080 1520 can1 message slot 2 standard id 0 can1 message slot 2 standard id 1 13-58 (c1msl2sid0) (c1msl2sid1) 13-59 h'0080 1522 can1 message slot 2 extended id 0 can1 message slot 2 extended id 1 13-60 (c1msl2eid0) (c1msl2eid1) 13-61 h'0080 1524 can1 message slot 2 extended id 2 can1 message slot 2 data length register 13-62 (c1msl2eid2) (c1msl2dlc) 13-63 h'0080 1526 can1 message slot 2 data 0 can1 message slot 2 data 1 13-64 (c1msl2dt0) (c1msl2dt1) 13-65 h'0080 1528 can1 message slot 2 data 2 can1 message slot 2 data 3 13-66 (c1msl2dt2) (c1msl2dt3) 13-67 h'0080 152a can1 message slot 2 data 4 can1 message slot 2 data 5 13-68 (c1msl2dt4) (c1msl2dt5) 13-69 h'0080 152c can1 message slot 2 data 6 can1 message slot 2 data 7 13-70 (c1msl2dt6) (c1msl2dt7) 13-71 h'0080 152e can1 message slot 2 timestamp 13-72 (c1msl2tsp) h'0080 1530 can1 message slot 3 standard id 0 can1 message slot 3 standard id 1 13-58 (c1msl3sid0) (c1msl3sid1) 13-59 h'0080 1532 can1 message slot 3 extended id 0 can1 message slot 3 extended id 1 13-60 (c1msl3eid0) (c1msl3eid1) 13-61 h'0080 1534 can1 message slot 3 extended id 2 can1 message slot 3 data length register 13-62 (c1msl3eid2) (c1msl3dlc) 13-63 h'0080 1536 can1 message slot 3 standard id 0 can1 message slot 3 standard id 1 13-64 (c1msl3dt0) (c1msl3dt1) 13-65 h'0080 1538 can1 message slot 3 data 2 can1 message slot 3 data 3 13-66 (c1msl3dt2) (c1msl3dt3) 13-67 h'0080 153a can1 message slot 3 data 4 can1 message slot 3 data 5 13-68 (c1msl3dt4) (c1msl3dt5) 13-69 h'0080 153c can1 message slot 3 data 6 can1 message slot 3 data 7 13-70 (c1msl3dt6) (c1msl3dt7) 13-71 h'0080 153e can1 message slot 3 timestamp 13-72 (c1msl3tsp) h'0080 1540 can1 message slot 4 standard id 0 can1 message slot 4 standard id 1 13-58 (c1msl4sid0) (c1msl4sid1) 13-59 h'0080 1542 can1 message slot 4 extended id 0 can1 message slot 4 extended id 1 13-60 (c1msl4eid0) (c1msl4eid1) 13-61 h'0080 1544 can1 message slot 4 extended id 2 can1 message slot 4 data length register 13-62 (c1msl4eid2) (c1msl4dlc) 13-63 h'0080 1546 can1 message slot 4 data 0 can1 message slot 4 data 1 13-64 (c1msl4dt0) (c1msl4dt1) 13-65 h'0080 1548 can1 message slot 4 data 2 can1 message slot 4 data 3 13-66 (c1msl4dt2) (c1msl4dt3) 13-67 h'0080 154a can1 message slot 4 data 4 can1 message slot 4 data 5 13-68 (c1msl4dt4) (c1msl4dt5) 13-69 h'0080 154c can1 message slot 4 data 6 can1 message slot 4 data 7 13-70 (c1msl4dt6) (c1msl4dt7) 13-71 h'0080 154e can1 message slot 4 timestamp 13-72 (c1msl4tsp) 3 3-30 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (20/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 1550 can1 message slot 5 standard id 0 can1 message slot 5 standard id 1 13-58 (c1msl5sid0) (c1msl5sid1) 13-59 h'0080 1552 can1 message slot 5 extended id 0 can1 message slot 5 extended id 1 13-60 (c1msl5eid0) (c1msl5eid1) 13-61 h'0080 1554 can1 message slot 5 extended id 2 can1 message slot 5 data length register 13-62 (c1msl5eid2) (c1msl5dlc) 13-63 h'0080 1556 can1 message slot 5 data 0 can1 message slot 5 data 1 13-64 (c1msl5dt0) (c1msl5dt1) 13-65 h'0080 1558 can1 message slot 5 data 2 can1 message slot 5 data 3 13-66 (c1msl5dt2) (c1msl5dt3) 13-67 h'0080 155a can1 message slot 5 data 4 can1 message slot 5 data 5 13-68 (c1msl5dt4) (c1msl5dt5) 13-69 h'0080 155c can1 message slot 5 data 6 can1 message slot 5 data 7 13-70 (c1msl5dt6) (c1msl5dt7) 13-71 h'0080 155e can1 message slot 5 timestamp 13-72 (c1msl5tsp) h'0080 1560 can1 message slot 6 standard id 0 can1 message slot 6 standard id 1 13-58 (c1msl6sid0) (c1msl6sid1) 13-59 h'0080 1562 can1 message slot 6 extended id 0 can1 message slot 6 extended id 1 13-60 (c1msl6eid0) (c1msl6eid1) 13-61 h'0080 1564 can1 message slot 6 extended id 2 can1 message slot 6 data length register 13-62 (c1msl6eid2) (c1msl6dlc) 13-63 h'0080 1566 can1 message slot 6 data 0 can1 message slot 6 data 1 13-64 (c1msl6dt0) (c1msl6dt1) 13-65 h'0080 1568 can1 message slot 6 data 2 can1 message slot 6 data 3 13-66 (c1msl6dt2) (c1msl6dt3) 13-67 h'0080 156a can1 message slot 6 data 4 can1 message slot 6 data 5 13-68 (c1msl6dt4) (c1msl6dt5) 13-69 h'0080 156c can1 message slot 6 data 6 can1 message slot 6 data 7 13-70 (c1msl6dt6) (c1msl6dt7) 13-71 h'0080 156e can1 message slot 6 timestamp 13-72 (c1msl6tsp) h'0080 1570 can1 message slot 7 standard id 0 can1 message slot 7 standard id 1 13-58 (c1msl7sid0) (c1msl7sid1) 13-59 h'0080 1572 can1 message slot 7 extended id 0 can1 message slot 7 extended id 1 13-60 (c1msl7eid0) (c1msl7eid1) 13-61 h'0080 1574 can1 message slot 7 extended id 2 can1 message slot 7 data length register 13-62 (c1msl7eid2) (c1msl7dlc) 13-63 h'0080 1576 can1 message slot 7 data 0 can1 message slot 7 data 1 13-64 (c1msl7dt0) (c1msl7dt1) 13-65 h'0080 1578 can1 message slot 7 data 2 can1 message slot 7 data 3 13-66 (c1msl7dt2) (c1msl7dt3) 13-67 h'0080 157a can1 message slot 7 data 4 can1 message slot 7 data 5 13-68 (c1msl7dt4) (c1msl7dt5) 13-69 h'0080 157c can1 message slot 7 data 6 can1 message slot 7 data 7 13-70 (c1msl7dt6) (c1msl7dt7) 13-71 h'0080 157e can1 message slot 7 timestamp 13-72 (c1msl7tsp) h'0080 1580 can1 message slot 8 standard id 0 can1 message slot 8 standard id 1 13-58 (c1msl8sid0) (c1msl8sid1) 13-59 h'0080 1582 can1 message slot 8 extended id 0 can1 message slot 8 extended id 1 13-60 (c1msl8eid0) (c1msl8eid1) 13-61 h'0080 1584 can1 message slot 8 extended id 2 can1 message slot 8 data length register 13-62 (c1msl8eid2) (c1msl8dlc) 13-63 h'0080 1586 can1 message slot 8 data 0 can1 message slot 8 data 1 13-64 (c1msl8dt0) (c1msl8dt1) 13-65 h'0080 1588 can1 message slot 8 data 2 can1 message slot 8 data 3 13-66 (c1msl8dt2) (c1msl8dt3) 13-67 h'0080 158a can1 message slot 8 data 4 can1 message slot 8 data 5 13-68 (c1msl8dt4) (c1msl8dt5) 13-69 h'0080 158c can1 message slot 8 data 6 can1 message slot 8 data 7 13-70 (c1msl8dt6) (c1msl8dt7) 13-71 h'0080 158e can1 message slot 8 timestamp 13-72 (c1msl8tsp) 3 3-31 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (21/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 1590 can1 message slot 9 standard id 0 can1 message slot 9 standard id 1 13-58 (c1msl9sid0) (c1msl9sid1) 13-59 h'0080 1592 can1 message slot 9 extended id 0 can1 message slot 9 extended id 1 13-60 (c1msl9eid0) (c1msl9eid1) 13-61 h'0080 1594 can1 message slot 9 extended id 2 can1 message slot 9 data length register 13-62 (c1msl9eid2) (c1msl9dlc) 13-63 h'0080 1596 can1 message slot 9 data 0 can1 message slot 9 data 1 13-64 (c1msl9dt0) (c1msl9dt1) 13-65 h'0080 1598 can1 message slot 9 data 2 can1 message slot 9 data 3 13-66 (c1msl9dt2) (c1msl9dt3) 13-67 h'0080 159a can1 message slot 9 data 4 can1 message slot 9 data 5 13-68 (c1msl9dt4) (c1msl9dt5) 13-69 h'0080 159c can1 message slot 9 data 6 can1 message slot 9 data 7 13-70 (c1msl9dt6) (c1msl9dt7) 13-71 h'0080 159e can1 message slot 9 timestamp 13-72 (c1msl9tsp) h'0080 15a0 can1 message slot 10 standard id 0 can1 message slot 10 standard id 1 13-58 (c1msl10sid0) (c1msl10sid1) 13-59 h'0080 15a2 can1 message slot 10 extended id 0 can1 message slot 10 extended id 1 13-60 (c1msl10eid0) (c1msl10eid1) 13-61 h'0080 15a4 can1 message slot 10 extended id 2 can1 message slot 10 data length register 13-62 (c1msl10eid2) (c1msl10dlc) 13-63 h'0080 15a6 can1 message slot 10 data 0 can1 message slot 10 data 1 13-64 (c1msl10dt0) (c1msl10dt1) 13-65 h'0080 15a8 can1 message slot 10 data 2 can1 message slot 10 data 3 13-66 (c1msl10dt2) (c1msl10dt3) 13-67 h'0080 15aa can1 message slot 10 data 4 can1 message slot 10 data 5 13-68 (c1msl10dt4) (c1msl10dt5) 13-69 h'0080 15ac can1 message slot 10 data 6 can1 message slot 10 data 7 13-70 (c1msl10dt6) (c1msl10dt7) 13-71 h'0080 15ae can1 message slot 10 timestamp 13-72 (c1msl10tsp) h'0080 15b0 can1 message slot 11 standard id 0 can1 message slot 11 standard id 1 13-58 (c1msl11sid0) (c1msl11sid1) 13-59 h'0080 15b2 can1 message slot 11 extended id 0 can1 message slot 11 extended id 1 13-60 (c1msl11eid0) (c1msl11eid1) 13-61 h'0080 15b4 can1 message slot 11 extended id 2 can1 message slot 11 data length register 13-62 (c1msl11eid2) (c1msl11dlc) 13-63 h'0080 15b6 can1 message slot 11 data 0 can1 message slot 11 data 1 13-64 (c1msl11dt0) (c1msl11dt1) 13-65 h'0080 15b8 can1 message slot 11 data 2 can1 message slot 11 data 3 13-66 (c1msl11dt2) (c1msl11dt3) 13-67 h'0080 15ba can1 message slot 11 data 4 can1 message slot 11 data 5 13-68 (c1msl11dt4) (c1msl11dt5) 13-69 h'0080 15bc can1 message slot 11 data 6 can1 message slot 11 data 7 13-70 (c1msl11dt6) (c1msl11dt7) 13-71 h'0080 15be can1 message slot 11 timestamp 13-72 (c1msl11tsp) h'0080 15c0 can1 message slot 12 standard id 0 can1 message slot 12 standard id 1 13-58 (c1msl12sid0) (c1msl12sid1) 13-59 h'0080 15c2 can1 message slot 12 extended id 0 can1 message slot 12 extended id 1 13-60 (c1msl12eid0) (c1msl12eid1) 13-61 h'0080 15c4 can1 message slot 12 extended id 2 can1 message slot 12 data length register 13-62 (c1msl12eid2) (c1msl12dlc) 13-63 h'0080 15c6 can1 message slot 12 data 0 can1 message slot 12 data 1 13-64 (c1msl12dt0) (c1msl12dt1) 13-65 h'0080 15c8 can1 message slot 12 data 2 can1 message slot 12 data 3 13-66 (c1msl12dt2) (c1msl12dt3) 13-67 h'0080 15ca can1 message slot 12 data 4 can1 message slot 12 data 5 13-68 (c1msl12dt4) (c1msl12dt5) 13-69 h'0080 15cc can1 message slot 12 data 6 can1 message slot 12 data 7 13-70 (c1msl12dt6) (c1msl12dt7) 13-71 h'0080 15ce can1 message slot 12 timestamp 13-72 (c1msl12tsp) 3 3-32 address space 3.4 internal ram and sfr areas 32176 group user?s manual (rev.1.01) sfr area register map (22/22) address +0 address +1 address see b0 b7 b8 b15 pages h'0080 15d0 can1 message slot 13 standard id 0 can1 message slot 13 standard id 1 13-58 (c1msl13sid0) (c1msl13sid1) 13-59 h'0080 15d2 can1 message slot 13 extended id 0 can1 message slot 13 extended id 1 13-60 (c1msl13eid0) (c1msl13eid1) 13-61 h'0080 15d4 can1 message slot 13 extended id 2 can1 message slot 13 data length register 13-62 (c1msl13eid2) (c1msl13dlc) 13-63 h'0080 15d6 can1 message slot 13 data 0 can1 message slot 13 data 1 13-64 (c1msl13dt0) (c1msl13dt1) 13-65 h'0080 15d8 can1 message slot 13 data 2 can1 message slot 13 data 3 13-66 (c1msl13dt2) (c1msl13dt3) 13-67 h'0080 15da can1 message slot 13 data 4 can1 message slot 13 data 5 13-68 (c1msl13dt4) (c1msl13dt5) 13-69 h'0080 15dc can1 message slot 13 data 6 can1 message slot 13 data 7 13-70 (c1msl13dt6) (c1msl13dt7) 13-71 h'0080 15de can1 message slot 13 timestamp 13-72 (c1msl13tsp) h'0080 15e0 can1 message slot 14 standard id 0 can1 message slot 14 standard id 1 13-58 (c1msl14sid0) (c1msl14sid1) 13-59 h'0080 15e2 can1 message slot 14 extended id 0 can1 message slot 14 extended id 1 13-60 (c1msl14eid0) (c1msl14eid1) 13-61 h'0080 15e4 can1 message slot 14 extended id 2 can1 message slot 14 data length register 13-62 (c1msl14eid2) (c1msl14dlc) 13-63 h'0080 15e6 can1 message slot 14 data 0 can1 message slot 14 data 1 13-64 (c1msl14dt0) (c1msl14dt1) 13-65 h'0080 15e8 can1 message slot 14 data 2 can1 message slot 14 data 3 13-66 (c1msl14dt2) (c1msl14dt3) 13-67 h'0080 15ea can1 message slot 14 data 4 can1 message slot 14 data 5 13-68 (c1msl14dt4) (c1msl14dt5) 13-69 h'0080 15ec can1 message slot 14 data 6 can1 message slot 14 data 7 13-70 (c1msl14dt6) (c1msl14dt7) 13-71 h'0080 15ee can1 message slot 14 timestamp 13-72 (c1msl14tsp) h'0080 15f0 can1 message slot 15 standard id 0 can1 message slot 15 standard id 1 13-58 (c1msl15sid0) (c1msl15sid1) 13-59 h'0080 15f2 can1 message slot 15 extended id 0 can1 message slot 15 extended id 1 13-60 (c1msl15eid0) (c1msl15eid1) 13-61 h'0080 15f4 can1 message slot 15 extended id 2 can1 message slot 15 data length register 13-62 (c1msl15eid2) (c1msl15dlc) 13-63 h'0080 15f6 can1 message slot 15 data 0 can1 message slot 15 data 1 13-64 (c1msl15dt0) (c1msl15dt1) 13-65 h'0080 15f8 can1 message slot 15 data 2 can1 message slot 15 data 3 13-66 (c1msl15dt2) (c1msl15dt3) 13-67 h'0080 15fa can1 message slot 15 data 4 can1 message slot 15 data 5 13-68 (c1msl15dt4) (c1msl15dt5) 13-69 h'0080 15fc can1 message slot 15 data 6 can1 message slot 15 data 7 13-70 (c1msl15dt6) (c1msl15dt7) 13-71 h'0080 15fe can1 message slot 15 timestamp 13-72 (c1msl15tsp) (use inhibited area) h'0080 3ffe (use inhibited area) | 3 3-33 address space 32176 group user?s manual (rev.1.01) 3.5 eit vector entry 3.5 eit vector entry the eit vector entry is located at the beginning of the internal rom/external extension areas. the branch instruction for jumping to the start address of each eit event processing handler is written here. note that it is the branch instruction and not the jump address itself that is written here. for details, see chapter 4, ?eit.? h'0000 0040 h'0000 0044 h'0000 0048 h'0000 004c h'0000 0050 h'0000 0054 h'0000 0058 h'0000 005c h'0000 0060 h'0000 0064 h'0000 0068 h'0000 006c h'0000 0070 h'0000 0074 h'0000 0078 h'0000 007c h'0000 0080 h'0000 0030 h'0000 0020 h'0000 0010 h'0000 0000 h'0000 0034 h'0000 0038 h'0000 003c h'0000 0024 h'0000 0028 h'0000 002c h'0000 0004 h'0000 0008 h'0000 000c h'0000 0014 h'0000 0018 h'0000 001c trap0 trap1 trap2 trap3 trap4 trap5 trap6 trap7 trap8 trap9 trap10 trap11 trap12 trap13 trap14 trap15 ae (address exception) ei (external interrupt) (note 1) ri (reset interrupt) sbi (system break interrupt) rie (reserved instruction exception) 031 note 1: when flash entry bit = 1 (flash e/w enable mode), the ei vector entry is located at h'0080 4000. figure 3.5.1 eit vector entry 3 3-34 address space 32176 group user?s manual (rev.1.01) 3.6 icu vector table the icu vector table is used by the internal interrupt controller of the microcomputer. this table has the addresses shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal peripheral i/os are set. for details, see chapter 5, ?interrupt controller.? icu vector table memory map (1/2) address +0 address +1 address b0 b7 b8 b15 h'0000 0094 mjt input interrupt 4 handler start address (a0?a15) h'0000 0096 mjt input interrupt 4 handler start address (a16?a31) h'0000 0098 mjt input interrupt 3 handler start address (a0?a15) h'0000 009a mjt input interrupt 3 handler start address (a16?a31) h'0000 009c mjt input interrupt 2 handler start address (a0?a15) h'0000 009e mjt input interrupt 2 handler start address (a16?a31) h'0000 00a0 mjt input interrupt 1 handler start address (a0?a15) h'0000 00a2 mjt input interrupt 1 handler start address (a16?a31) h'0000 00a4 h'0000 00a6 h'0000 00a8 mjt output interrupt 7 handler start address (a0?a15) h'0000 00aa mjt output interrupt 7 handler start address (a16?a31) h'0000 00ac mjt output interrupt 6 handler start address (a0?a15) h'0000 00ae mjt output interrupt 6 handler start address (a16?a31) h'0000 00b0 mjt output interrupt 5 handler start address (a0?a15) h'0000 00b2 mjt output interrupt 5 handler start address (a16?a31) h'0000 00b4 mjt output interrupt 4 handler start address (a0?a15) h'0000 00b6 mjt output interrupt 4 handler start address (a16?a31) h'0000 00b8 mjt output interrupt 3 handler start address (a0?a15) h'0000 00ba mjt output interrupt 3 handler start address (a16?a31) h'0000 00bc mjt output interrupt 2 handler start address (a0?a15) h'0000 00be mjt output interrupt 2 handler start address (a16?a31) h'0000 00c0 mjt output interrupt 1 handler start address (a0?a15) h'0000 00c2 mjt output interrupt 1 handler start address (a16?a31) h'0000 00c4 mjt output interrupt 0 handler start address (a0?a15) h'0000 00c6 mjt output interrupt 0 handler start address (a16?a31) h'0000 00c8 dma0?4 interrupt handler start address (a0?a15) h'0000 00ca dma0?4 interrupt handler start address (a16?a31) h'0000 00cc sio1 receive interrupt handler start address (a0?a15) h'0000 00ce sio1 receive interrupt handler start address (a16?a31) h'0000 00d0 sio1 transmit interrupt handler start address (a0?a15) h'0000 00d2 sio1 transmit interrupt handler start address (a16?a31) h'0000 00d4 sio0 receive interrupt handler start address (a0?a15) h'0000 00d6 sio0 receive interrupt handler start address (a16?a31) 3.6 icu vector table 3 3-35 address space 32176 group user?s manual (rev.1.01) 3.6 icu vector table icu vector table memory map (2/2) address +0 address +1 address b0 b7 b8 b15 h'0000 00d8 sio0 transmit interrupt handler start address (a0?a15) h'0000 00da sio0 transmit interrupt handler start address (a16?a31) h'0000 00dc a-d0 conversion interrupt handler start address (a0?a15) h'0000 00de a-d0 conversion interrupt handler start address (a16?a31) h'0000 00e0 h'0000 00e2 h'0000 00e4 h'0000 00e6 h'0000 00e8 dma5?9 interrupt handler start address (a0?a15) h'0000 00ea dma5?9 interrupt handler start address (a16?a31) h'0000 00ec sio2, 3 transmit/receive interrupt handler start address (a0?a15) h'0000 00ee sio2, 3 transmit/receive interrupt handler start address (a16?a31) h'0000 00f0 rtd interrupt handler start address (a0?a15) h'0000 00f2 rtd interrupt handler start address (a16?a31) h'0000 00f4 h'0000 00f6 h'0000 00f8 h'0000 00fa h'0000 00fc h'0000 00fe h'0000 0100 h'0000 0102 h'0000 0104 h'0000 0106 h'0000 0108 h'0000 010a h'0000 010c can0 transmit/receive & error interrupt handler start address (a0?a15) h'0000 010e can0 transmit/receive & error interrupt handler start address (a16?a31) h'0000 0110 can1 transmit/receive & error interrupt handler start address (a0?a15) h'0000 0112 can1 transmit/receive & error interrupt handler start address (a16?a31) 3 3-36 address space 32176 group user?s manual (rev.1.01) 3.7 notes about address space 3.7 notes about address space ? virtual flash emulation function the microcomputer has the function to map up to two 8-kbyte memory blocks of the internal ram into areas of the internal flash memory (l banks) that are divided in 8-kbyte units, as well as to map up to two 4-kbyte memory blocks of the internal ram into areas of the internal flash memory (s banks) that are divided in 4-kbyte units. this function is referred to as the virtual flash emulation function. for details about this function, refer to section 6.6, ?virtual flash emulation function.? chapter 4 eit 4.1 outline of eit 4.2 eit events 4.3 eit processing procedure 4.4 eit processing mechanism 4.5 acceptance of eit events 4.6 saving and restoring the pc and psw 4.7 eit vector entry 4.8 exception processing 4.9 interrupt processing 4.10 trap p rocessing 4.11 eit priority levels 4.12 example of eit processing 4.13 precautions on eit 4 4-2 eit 32176 group user?s manual (rev.1.01) 4.1 outline of eit if some event occurs when the cpu is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. events like this one are referred to by a generic name as eit (exception, interrupt and trap). (1) exception this is an event related to the context being executed. it is generated by an error or violation during instruction execution. this type of event includes address exception (ae) and reserved instruction exception (rie) . (2) interrupt this is an event generated irrespective of the context being executed. it is generated by a hardware-derived signal from an external source. this type of event includes reset interrupt (ri), system break interrupt (sbi) and external interrupt (ei). (3) trap this refers to a software interrupt generated by executing a trap instruction. this type of event is intentionally generated in a program as in the os?s system call by the programmer. 4.1 outline of eit figure 4.1.1 classification of eits eit exception (exception) reserved instruction exception (rie) address exception (ae) reset interrupt (ri) system break interrupt (sbi) external interrupt (ei) tra p (trap) interrupt (interrupt) tra p (tra p ) 4 4-3 eit 32176 group user?s manual (rev.1.01) 4.2 eit events 4.2 eit events 4.2.1 exception (1) reserved instruction exception (rie) reserved instruction exception (rie) occurs when execution of a reserved instruction (unimplemented instruction) is detected. (2) address exception (ae) address exception (ae) occurs when an attempt is made to access a misaligned address in load or store instructions. 4.2.2 interrupt (1) reset interrupt (ri) reset interrupt (ri) is always accepted by entering the reset# signal. the reset interrupt is assigned the highest priority. (2) system break interrupt (sbi) system break interrupt (sbi) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. this interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) external interrupt (ei) external interrupt (ei) is requested from internal peripheral i/os managed by the interrupt controller. the internal interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state. 4.2.3 trap traps are software interrupts which are generated by executing the trap instruction. sixteen distinct vector addresses are provided corresponding to trap instruction operands 0?15. 4 4-4 eit 32176 group user?s manual (rev.1.01) 4.3 eit processing procedure eit processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (eit handlers). the procedure for processing eits when accepted, except for a reset interrupt, is shown below. 4.3 eit processing procedure figure 4.3.1 outline of the eit processing procedure instruction a pc bpc psw (b)psw eit vector entry eit handler except for sbi rte instruction program suspended and eit request accepted instruction processing-canceled type (rie, ae) instruction processing-completed type (ei, trap) program execution restarted eit request generated hardware preprocessing bpc, psw and general-purpose registers are saved to the stack branch instruction general-purpose registers, psw and bpc are restored from the stack hardware postprocessing (sbi) program terminated or system is reset user-created eit handler (b)psw psw bpc pc processing by handler note 1: (b)psw indicates the bpsw field for the psw register. (note 1) sbi (system break interrupt processing) instruction b instruction c instruction c instruction d 4 4-5 eit 32176 group user?s manual (rev.1.01) when an eit is accepted, the cpu branches to the eit vector after hardware preprocessing (as will be described later). the eit vector has an entry address assigned for each eit. this is where the bra (branch) instruction for the eit handler (not the jump address itself) is written. in the hardware preprocessing, the content of the pc and psw registers is transferred to the backup register (bpc register and bpsw field in the psw register). other necessary operations must be performed in the user-created eit handler. these include saving the bpc register and psw register (including the bpsw field) and the general-purpose registers to be used in the eit handler to the stack. in addition, the accumulator must be saved to the stack as necessary. remember that all these registers must be saved to the stack in a program by the user. when processing by the eit handler is completed, restore the saved registers from the stack and finally execute the rte instruction. control is thereby returned from the eit processing to the program that was being executed when the eit occurred. (this does not apply to the system break interrupt, however.) in the hardware postprocessing, the content of the backup register (bpc register and bpsw field in the psw register) is returned to the pc and psw registers. note that the values stored in the bpc and the psw register?s bpsw field after executing the rte instruction are undefined. 4.3 eit processing procedure 4 4-6 eit 32176 group user?s manual (rev.1.01) 4.4 eit processing mechanism the eit processing mechanism consists of the m32r cpu core and the interrupt controller for internal peripheral i/ os. it also has the backup registers for the pc and psw (the bpc register and the bpsw field in the psw register). the eit processing mechanism is shown below. 4.4 eit processing mechanism figure 4.4.1 eit processing mechanism interrupt controller (icu) sbi ei internal peripheral i/os reset# ri ae, rie, trap ie flag (psw) m32r cpu core sbi# low high priority sbi ei ri m32r/ecu psw register psw bpsw bpc register pc register 4 4-7 eit 32176 group user?s manual (rev.1.01) 4.5 acceptance of eit events when an eit event occurs, the cpu suspends the program it has hitherto been executing and branches to eit processing by the relevant handler. conditions under which each eit event occurs and the timing at which they are accepted are shown below. table 4.5.1 acceptance of eit events eit event type of processing acceptance timing values set in bpc register reserved instruction in struction processing- during instruction execution pc value of the instruction that exception (rie) canceled type generated rie address exception (ae) instruction processing- during instruction execution pc value of the instruction that canceled type generated ae reset interrupt (ri) in struction processing- each machine cycle undefined value aborted type system break interrupt instruction processing- break in instructions pc value of the next instruction (sbi) completed type (word boundary only) external interrupt (ei) instruction processing- break in instructions pc value of the next instruction completed type (word boundary only) trap (trap) in struction processing- break in instructions pc value of trap instruction + 4 completed type 4.6 saving and restoring the pc and psw the following describes operation of the microcomputer at the time when it accepts an eit and when it executes the rte instruction. (1) hardware preprocessing when an eit is accepted [1] save the psw register?s sm, ie and c bits in its backup field. bsm [2] update the psw register?s sm, ie and c bits sm [3] save the pc register bpc [4] set the vector address in the pc register branches to the eit vector and executes the branch (bra) instruction written in it, thereby transferring control to the user-created eit handler. (2) hardware postprocessing when the rte instruction is executed [a] restore the psw register?s sm, ie and c bits from its backup field. sm [b] restore the pc register from the bpc register. pc 4.5 acceptance of eit events 4 4-8 eit 32176 group user?s manual (rev.1.01) 4.6 saving and restoring the pc and psw psw bpc pc when eit is accepted when rte instruction is executed [1] saving the sm, ie and c bits bsm bie bc sm ie c [2] updating the sm, ie and c bits sm ie c unchanged or 0 0 0 [3] saving the pc bpc pc [4] setting the vector address in the pc pc vector address [b] restoring the pc from the bpc register the value stored in the bpc register after executing the rte instruction is undefined. [a] restoring the sm, ie and c bits from the backup field sm ie c the values stored in the bsm, bie and bc bits after executing the rte instruction are undefined. bsm bie bc [1] [a] [b] [2] [3] [4] figure 4.6.1 saving and restoring the pc and psw 16 17 23 24 25 31(lsb) 15 8 7 0(msb) sm ie c bc bsm bie 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psw bpsw field psw field 4 4-9 eit 32176 group user?s manual (rev.1.01) 4.7 eit vector entry the eit vector entry is located in the user space beginning with the address h?0000 0000. the table below lists the eit vector entry. table 4.7.1 eit vector entry name abbreviation vector address sm ie bpc reset interrupt ri h'0000 0000 (note 1) 0 0 undefined system break sbi h'0000 0010 0 0 pc of the next instruction interrupt reserved instruction rie h'0000 0020 unchanged 0 pc of the instruction that generated rie exception address exception ae h'0000 0030 unchanged 0 pc of the instruction that generated ae trap trap0 h'0000 0040 unchanged 0 pc of trap instruction + 4 trap1 h'0000 0044 unchanged 0 pc of trap instruction + 4 trap2 h'0000 0048 unchanged 0 pc of trap instruction + 4 trap3 h'0000 004c unchanged 0 pc of trap instruction + 4 trap4 h'0000 0050 unchanged 0 pc of trap instruction + 4 trap5 h'0000 0054 unchanged 0 pc of trap instruction + 4 trap6 h'0000 0058 unchanged 0 pc of trap instruction + 4 trap7 h'0000 005c unchanged 0 pc of trap instruction + 4 trap8 h'0000 0060 unchanged 0 pc of trap instruction + 4 trap9 h'0000 0064 unchanged 0 pc of trap instruction + 4 trap10 h'0000 0068 unchanged 0 pc of trap instruction + 4 trap11 h'0000 006c unchanged 0 pc of trap instruction + 4 trap12 h'0000 0070 unchanged 0 pc of trap instruction + 4 trap13 h'0000 0074 unchanged 0 pc of trap instruction + 4 trap14 h'0000 0078 unchanged 0 pc of trap instruction + 4 trap15 h'0000 007c unchanged 0 pc of trap instruction + 4 external interrupt ei h'0000 0080 (note 2) 0 0 pc of the next instruction note 1: during boot mode, the cpu starts executing the boot program after exiting the reset state. for details, see section 6.5, ?programming the internal flash memory.? note 2: during flash e/w enable mode, this vector address is moved to the beginning of the internal ram (address h?0080 4000). for details, see section 6.5, ?programming the internal flash memory.? 4.7 eit vector entry 4 4-10 eit 32176 group user?s manual (rev.1.01) 4.8 exception processing 4.8 exception processing 4.8.1 reserved instruction exception (rie) [occurrence conditions] reserved instruction exception (rie) occurs when a reserved instruction (unimplemented instruction) is detected. instruction check is performed on the op-code part of the instruction. when a reserved instruction exception occurs, the instruction that generated it is not executed. if an exter- nal interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [eit processing] (1) saving sm, ie and c bits the psw register?s sm, ie and c bits are saved to the respective backup bits: bsm, bie and bc. bsm (2) updating sm, ie and c bits the psw register?s sm, ie and c bits are updated as shown below. sm (3) saving the pc the pc value of the instruction that generated the reserved instruction exception is set in the bpc register. for example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the bpc register. similarly, if the instruction that generated the reserved instruction exception is at address 6, the value 6 is set in the bpc register. in this case, the value of the bpc register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (bpc[30] = 0) or not on a word boundary (bpc[30] = 1). however, in either case of the above, the address to which the rte instruction returns after the eit handler has terminated is address 4. (this is because the 2 low-order address bits are cleared to ?00? when returned to the pc.) figure 4.8.1 example of a return address for reserved instruction exception (rie) h'00 address rie occurred h'04 h'08 h'0c +0 +1 +2 +3 h'00 address rie occurred h'04 h'08 h'0c +0 +1 +2 +3 return address bpc h'06 bpc h'04 return address 4 4-11 eit 32176 group user?s manual (rev.1.01) 4.8 exception processing (4) branching to the eit vector entry the cpu branches to the address h?0000 0020 in the user space. this is the last operation performed in hardware preprocessing. (5) jumping from the eit vector entry to the user-created handler the cpu executes the bra instruction written by the user at the address h?0000 0020 of the eit vector entry to jump to the start address of the user-created handler. at the beginning of the user-created eit handler, first save the bpc and psw registers and the necessary general-purpose registers to the stack. also, save the accumulator as necessary. (6) returning from the eit handler at the end of the eit handler, restore the saved registers from the stack and execute the rte instruction. when the rte instruction is executed, hardware postprocessing is automatically performed. at this time, the cpu restarts from a word-boundary instruction including the instruction that generated a rie (see figure 4.8.1). except when using reserved instruction exceptions intentionally, occurrence of a reserved instruc- tion exception suggests that the system has some fatal fault already existing in it. in such a case, therefore, do not return from the reserved instruction exception handler to the program that was being executed when the exception occurred. 4 4-12 eit 32176 group user?s manual (rev.1.01) 4.8 exception processing figure 4.8.2 example of a return address for address exception (ae) h'00 address ae occurred h'04 h'08 h'0c +0 +1 +2 +3 h'00 address ae occurred h'04 h'08 h'0c +0 +1 +2 +3 bpc h'06 bpc h'04 return address return address 4.8.2 address exception (ae) [occurrence conditions] address exception (ae) occurs when an attempt is made to access a misaligned address in load or store instructions. the following lists the combination of instructions and accessed addresses that may cause address exceptions to occur. ? two low-order address bits accessed in the ldh, lduh or sth instruction are ?01? or ?11? ? two low-order address bits accessed in the ld, st, lock or unlock instruction are ?01,? ?10? or ?11? when an address exception occurs, memory access by the instruction that generated the exception is not performed. if an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [eit processing] (1) saving sm, ie and c bits the psw register?s sm, ie and c bits are saved to the respective backup bits: bsm, bie and bc. bsm (2) updating sm, ie and c bits the psw register?s sm, ie and c bits are updated as shown below. sm (3) saving the pc the pc value of the instruction that generated the address exception is set in the bpc register. for example, if the instruction that generated the address exception is at address 4, the value 4 is set in the bpc register. similarly, if the instruction that generated the address exception is at address 6, the value 6 is set in the bpc register. in this case, the value of the bpc register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (bpc[30] = 0) or not on a word boundary (bpc[30] = 1). however, in either case of the above, the address to which the rte instruction returns after the eit handler has terminated is address 4. (this is because the 2 low-order address bits are cleared to ?00? when returned to the pc.) 4 4-13 eit 32176 group user?s manual (rev.1.01) 4.8 exception processing (4) branching to the eit vector entry the cpu branches to the address h?0000 0030 in the user space. this is the last operation performed in hardware preprocessing. (5) jumping from the eit vector entry to the user-created handler the cpu executes the bra instruction written by the user at the address h?0000 0030 of the eit vector entry to jump to the start address of the user-created handler. at the beginning of the user-created eit handler, first save the bpc and psw registers and the necessary general-purpose registers to the stack. also, save the accumulator as necessary. (6) returning from the eit handler at the end of the eit handler, restore the saved registers from the stack and execute the rte instruction. when the rte instruction is executed, hardware postprocessing is automatically performed. at this time, the cpu restarts from a word-boundary instruction including the instruction that generated an ae (see figure 4.8.2). except when using address exceptions intentionally, occurrence of an address exception suggests that the system has some fatal fault already existing in it. in such a case, therefore, do not return from the address exception handler to the program that was being executed when the exception occurred. 4 4-14 eit 32176 group user?s manual (rev.1.01) 4.9 interrupt processing 4.9 interrupt processing 4.9.1 reset interrupt (ri) [occurrence conditions] a reset interrupt is accepted in machine cycle by pulling the reset# input signal low. the reset interrupt is assigned the highest priority among all eits. [eit processing] (1) initializing sm, ie and c bits the psw register?s sm, ie and c bits are initialized as shown below. sm (2) branching to the eit vector entry the cpu branches to the address h?0000 0000 in the user space. however, when operating in boot mode, the cpu jumps to the boot program. for details, see section 6.5, ?programming the internal flash memory.? (3) jumping from the eit vector entry to the user program the cpu executes the instruction written by the user at the address h?0000 0000 of the eit vector entry. in the reset vector entry, be sure to initialize the psw and spi registers before jumping to the start address of the user program. 4 4-15 eit 32176 group user?s manual (rev.1.01) 4.9.2 system break interrupt (sbi) system break interrupt (sbi) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. the system break interrupt cannot be masked by the psw register ie bit. therefore, the system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. also, this interrupt must be used on condition that after processing by the sbi handler, control will not return to the program that was being executed when the system break interrupt occurred. [occurrence conditions] a system break interrupt is accepted by a falling edge on sbi# input pin. (the system break interrupt cannot be masked by the psw register ie bit.) in no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (for 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) note also that because of the instruction processing-completed type, a system break interrupt is accepted after the instruction is completed. 4.9 interrupt processing 16-bit instruction order in which instructions are executed 32-bit instruction address 1000 address 1002 address 1004 address 1008 interrupt may be accepted interrupt cannot be accepted 16-bit instruction interrupt may be accepted interrupt may be accepted figure 4.9.1 timing at which system break interrupt (sbi) is accepted 4 4-16 eit 32176 group user?s manual (rev.1.01) [eit processing] (1) saving sm, ie and c bits the psw register?s sm, ie and c bits are saved to the respective backup bits: bsm, bie and bc. bsm (2) updating sm, ie and c bits the psw register?s sm, ie and c bits are updated as shown below. sm (3) saving the pc the content of the pc register (always on word boundary) is saved to the bpc register. if the interrupt was detected in a branch instruction, then the next instruction is one that exists at the jump address. (4) branching to the eit vector entry the cpu branches to the address h?0000 0010 in the user space. this is the last operation performed in hardware preprocessing. (5) jumping from the eit vector entry to the user-created handler the cpu executes the bra instruction written by the user at the address h?0000 0010 of the eit vector entry to jump to the start address of the user-created handler. the system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. also, this interrupt must be used on condition that after processing by the sbi handler, control will not return to the program that was being executed when the system break interrupt occurred. 4.9 interrupt processing 4 4-17 eit 32176 group user?s manual (rev.1.01) figure 4.9.2 timing at which external interrupt (ei) is accepted 4.9.3 external interrupt (ei) an external interrupt is generated upon an interrupt request which is output by the microcomputer?s internal interrupt controller. the interrupt controller manages interrupt requests by assigning each one of seven priority levels. for details, see chapter 5, ?interrupt controller.? for details about the interrupt request sources, see each section in which the relevant internal peripheral i/o is described. [occurrence conditions] external interrupts are managed by the microcomputer?s internal interrupt controller based on interrupt requests from each internal peripheral i/o, and are sent to the cpu via the interrupt controller. the cpu checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is de- tected and the psw register ie flag = "1", accepts it as an external interrupt. in no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (for 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) 4.9 interrupt processing 16-bit instruction order in which instructions are executed 32-bit instruction address 1000 address 1002 address 1004 address 1008 interrupt may be accepted interrupt cannot be accepted 16-bit instruction interrupt may be accepted interrupt may be accepted 4 4-18 eit 32176 group user?s manual (rev.1.01) 4.9 interrupt processing [eit processing] (1) saving sm, ie and c bits the psw register?s sm, ie and c bits are saved to the respective backup bits: bsm, bie and bc. bsm (2) updating sm, ie and c bits the psw register?s sm, ie and c bits are updated as shown below. sm (3) saving the pc the content of the pc register (always on word boundary) is saved to the bpc register. (4) branching to the eit vector entry the cpu branches to the address h?0000 0080 in the user space. however, when operating in flash e/w enable mode, the cpu goes to the beginning of the internal ram (address h?0080 4000). (for details, see section 6.5, ?programming the internal flash memory.?) this is the last operation performed in hardware preprocessing. (5) jumping from the eit vector entry to the user-created handler the cpu executes the bra instruction written by the user at the address h?0000 0080 of the eit vector entry to jump to the start address of the user-created handler. at the beginning of the user-created eit handler, first save the bpc and psw registers and the necessary general-purpose registers to the stack. also, save the accumulator as necessary. (6) returning from the eit handler at the end of the eit handler, restore the saved registers from the stack and execute the rte instruction. when the rte instruction is executed, hardware postprocessing is automatically performed. 4 4-19 eit 32176 group user?s manual (rev.1.01) figure 4.10.1 example of a return address for trap (trap) h'00 address h'04 h'08 h'0c +0 +1 +2 +3 h'00 address h'04 h'08 h'0c +0 +1 +2 +3 bpc h'0a bpc h'08 trap instruction return address return address trap instruction 4.10 trap processing 4.10.1 trap [occurrence conditions] traps are software interrupts which are generated by executing the trap instruction. sixteen traps are generated, each corresponding to one of trap instruction operands 0?15. accordingly, sixteen vector en- tries are provided. [eit processing] (1) saving sm, ie and c bits the psw register?s sm, ie and c bits are saved to the respective backup bits: bsm, bie and bc. bsm (2) updating sm, ie and c bits the psw register?s sm, ie and c bits are updated as shown below. sm (3) saving the pc when the trap instruction is executed, the pc value of trap instruction + 4 is set in the bpc register. for example, if the trap instruction is located at address 4, the value h?08 is set in the bpc register. similarly, if the trap instruction is located at address 6, the value h?0a is set in the bpc register. the value of the bpc register bit 30 indicates whether the trap instruction resides on a word boundary (bpc[30] = 0) or not on a word boundary (bpc[30] = 1). however, in either case of the above, the address to which the rte instruction returns after the eit handler has terminated is address 8. (this is because the 2 low-order address bits are cleared to ?00? when returned to the pc.) 4.10 trap processing 4 4-20 eit 32176 group user?s manual (rev.1.01) 4.10 trap processing (4) branching to the eit vector entry the cpu branches to the addresses h?0000 0040?h?0000 007c in the user space. this is the last operation performed in hardware preprocessing. (5) jumping from the eit vector entry to the user-created handler the cpu executes the bra instruction written by the user at the addresses h?0000 0040?h?0000 007c of the eit vector entry to jump to the start address of the user-created handler. at the beginning of the user- created eit handler, first save the bpc and psw registers and the necessary general-purpose registers to the stack. also, save the accumulator as necessary. (6) returning from the eit handler at the end of the eit handler, restore the saved registers from the stack and execute the rte instruction. when the rte instruction is executed, hardware postprocessing is automatically performed. 4 4-21 eit 32176 group user?s manual (rev.1.01) 4.11 eit priority levels the table below lists the priority levels of eit events. when two or more eits occur simultaneously, the event with the highest priority is accepted first. table 4.11.1 priority of eit events and how returned from eit priority eit event type of processing values set in bpc register 1 (highest) reset inter rupt (ri) instruction processing-aborted type undefined 2 address exception (ae) instruction processing-canceled type pc of the instruction that generated ae reserved instruction instruction processing-canceled type pc of the instruction that exception (rie) generated rie trap (trap) instruction processing-completed type trap instruction + 4 3 system break interrupt instruction processing-completed type pc of the next instruction (sbi) 4 external interrupt (ei) instruction processing-completed type pc of the next instruction note that for external interrupt (ei), the priority levels of interrupt requests from each peripheral i/o are set by the microcomputer?s internal interrupt controller. for details, see chapter 5, ?interrupt controller.? 4.11 eit priority levels 4 4-22 eit 32176 group user?s manual (rev.1.01) 4.12 example of eit processing 4.12 example of eit processing (1) when rie, ae, sbi, ei or trap occurs singly figure 4.12.1 processing of events when rie, ae, sbi, ei or trap occurs singly (2) when rie, ae or trap and ei occur simultaneously figure 4.12.2 processing of events when rie, ae or trap and ei occur simultaneously rte instruction ie = 0 rie, ae or trap is accepted first. bpc register = return address a ie = 1 rie, ae or trap and ei occur simultaneously return address a: ie = 1 ie = 0 ie = 1 rte instruction : eit handler ei is accepted next. bpc register = return address a rte instruction ie = 0 ie = 1 bpc register = return address a ie = 1 rie, ae, sbi, ei or trap occurs singly return address a: if ie = 0, no events but reset and sbi are accepted. : eit handler 4 4-23 eit 32176 group user?s manual (rev.1.01) 4.12 example of eit processing figure 4.12.3 example of eit processing bra instruction rte eit handler eit vector entry program being executed save bpc to the stack save psw to the stack save general-purpose registers to the stack processing by eit handler restore general-purpose registers from the stack restore psw from the stack restore bpc from the stack eit event occurs (sbi) system break interrupt (sbi) processing program terminated or system reset (other than sbi) pc bpc psw (b)psw hardware preprocessing hardware postprocessing (b)psw psw bpc pc (note 1) (note 1) note 1: indicates saving and restoring the psw register bits between its psw and bpsw fields. 4 4-24 eit 32176 group user?s manual (rev.1.01) 4.13 precautions on eit 4.13 precautions on eit the address exception (ae) requires caution because if one of the instructions that use ?register indirect + register update? addressing mode (following three) generates an address exception when it is executed, the values of the registers to be automatically updated (rsrc and rsrc2) become undefined. except that the values of rsrc and rsrc2 become undefined, these instructions behave the same way as when used in other addressing modes. ? applicable instructions ld rdest, @rsrc+ st rsrc1, @-rsrc2 st rsrc1, @+rsrc2 if the above case applies, consider the fact that the register values become undefined when you design the processing to be performed after executing said instructions. (if an address exception occurs, it means that the system has some fatal fault already existing in it. therefore, address exceptions must be used on condition that control will not be returned from the address exception handler to the program that was being executed when the exception occurred.) chapter 5 interrupt controller (icu) 5.1 outline of the interrupt controller 5.2 icu related registers 5.3 interrupt request sources in internal peripheral i/o 5.4 icu vector table 5.5 description of interrupt operation 5.6 description of system break interrupt (sbi) operation 5 5-2 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.1 outline of the interrupt controller the interrupt controller (icu) manages maskable interrupts from internal peripheral i/os and a system break interrupt (sbi). the maskable interrupts from internal peripheral i/os are sent to the m32r cpu as external interrupts (ei). the maskable interrupts from internal peripheral i/os are managed by assigning them one of eight priority levels including an interrupt-disabled state. if two or more interrupt requests with the same priority level occur at the same time, their priorities are resolved by predetermined hardware priority. the source of an interrupt request generated in internal peripheral i/os is identified by reading the relevant interrupt status register provided for internal peripheral i/os. on the other hand, the system break interrupt (sbi) is recognized when a falling edge occurs on the sbi# signal input pin. this interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the psw register ie bit status. after processing of an sbi, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. specifications of the interrupt controller are outlined below. table 5.1.1 outline of the interrupt controller (icu) item specification interrupt request source maskable interrupt requests from internal peripheral i/os: 23 sources (note 1) system break interrupt request: 1 source (input from sbi# pin) priority management 8 priority levels including an interrupt-disabled state (however, interrupts with the same priority level have their priorities resolved by fixed hardware priority.) note 1: this is the number of interrupt requests divided into groups. there are actually a total of 123 interrupt request sources when counted individually. 5.1 outline of the interrupt controller 5 5-3 interrupt controller (icu) 32176 group user?s manual (rev.1.01) interrupt vector register (ivect) interrupt request mask register (imask) new_imask external interrupt (ei) request generated (maskable) imask compari- son ilevel system break interrupt (sbi) request generated (nonmaskable) sbi# ei sbi interrupt controller interrupt control register sbi control register (sbicr) sbireq ireq ireq ireq ireq ireq ireq peripheral circuits edge interrupt control circuit edge edge level interrupt request interrupt request interrupt request level level to the cpu core to the cpu core interrupt control circuit interrupt control circuit priority resolved by interrupt priority levels set priority resolved by fixed hardware priority figure 5.1.1 block diagram of the interrupt controller 5.1 outline of the interrupt controller 5 5-4 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.2 icu related registers 5.2 icu related registers the diagram below shows a register map associated with the interrupt controller (icu). icu related register map address +0 address +1 address see pages b0 b7 b8 b15 h'0080 0000 interrupt vector register 5-5 (ivect) h'0080 0002 (use inhibited area) h'0080 0004 interrupt request mask register (use inhibited area) 5-6 (imask) h'0080 0006 sbi control register (use inhibited area) 5-7 (sbicr) (use inhibited area) h'0080 0060 can0 transmit/receive & error interrupt control register (use inhibited area) 5-8 (ican0cr) h'0080 0062 (use inhibited area) h'0080 0064 (use inhibited area) h'0080 0066 (use inhibited area) rtd interrupt control register 5-8 (irtdcr) h'0080 0068 sio2,3 transmit/receive interrupt control register dma5?9 interrupt control register 5-8 (isio23cr) (idma59cr) h'0080 006a (use inhibited area) h'0080 006c a-d0 conversion interrupt control register sio0 transmit interrupt control register 5-8 (iad0ccr) (isio0txcr) h'0080 006e sio0 receive interrupt control register sio1 transmit interrupt control register 5-8 (isio0rxcr) (isio1txcr) h'0080 0070 sio1 receive interrupt control register dma0?4 interrupt control register 5-8 (isio1rxcr) (idma04cr) h'0080 0072 mjt output interrupt control register 0 mjt output interrupt control register 1 5-8 (imjtocr0) (imjtocr1) h'0080 0074 mjt output interrupt control register 2 mjt output interrupt control register 3 5-8 (imjtocr2) (imjtocr3) h'0080 0076 mjt output interrupt control register 4 mjt output interrupt control register 5 5-8 (imjtocr4) (imjtocr5) h'0080 0078 mjt output interrupt control register 6 mjt output interrupt control register 7 5-8 (imjtocr6) (imjtocr7) h'0080 007a (use inhibited area) mjt input interrupt control register 1 5-8 (imjticr1) h'0080 007c mjt input interrupt control register 2 mjt input interrupt control register 3 5-8 (imjticr2) (imjticr3) h'0080 007e mjt input interrupt control register 4 can1 transmit/receive & error interrupt control register 5-8 (imjticr4) (ican1cr) | 5 5-5 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.2 icu related registers 5.2.1 interrupt vector register interrupt vector register (ivect) 5 5-6 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.2 icu related registers 5.2.2 interrupt request mask register interrupt request mask register (imask) 5 5-7 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.2 icu related registers 5.2.3 sbi (system break interrupt) control register sbi (system break interrupt) control register (sbicr) 5 5-8 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.2 icu related registers 5.2.4 interrupt control registers can0 transmit/receive & error interrupt control register (ican0cr) 5 5-9 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 9 1011121314b15) (b8 123456b7 b0 ilevel ire q 0 111 0 0 0 0 5 5-10 interrupt controller (icu) 32176 group user?s manual (rev.1.01) (2) ilevel (interrupt priority level) (bits 5?7 or bits 13?15) these bits set the priority levels of interrupt requests from each internal peripheral i/o. set these bits to ?111? to disable or any value ?000? through ?110? to enable the interrupt from some internal peripheral i/o. when an interrupt occurs, the interrupt controller resolves priority between this interrupt and other interrupt sources based on ilevel settings and finally compares priority with the imask value to determine whether to forward an ei request to the cpu or keep the interrupt request pending. the table below shows the relationship between ilevel settings and the imask values at which interrupts are accepted. table 5.2.1 ilevel settings and accepted imask values ilevel values set imask values at which interrupts are accepted 0 (ilevel = "000") accepted when imask is 1?7 1 (ilevel = "001") accepted when imask is 2?7 2 (ilevel = "010") accepted when imask is 3?7 3 (ilevel = "011") accepted when imask is 4?7 4 (ilevel = "100") accepted when imask is 5?7 5 (ilevel = "101") accepted when imask is 6?7 6 (ilevel = "110") accepted when imask is 7 7 (ilevel = "111") not accepted (interrupts disabled) 5.2 icu related registers figure 5.2.1 configuration of the interrupt control register (edge-recognized type) interrupt request from each internal peripheral i/o interrupt enabled ilevel (levels 0-7) data bus b5-7 or b13-15 3 f/f set set/clear ireq interrupt priority resolving circuit f/f reset ivect read imask write clear to the cpu core b3 or b11 set ei interrupt request from each group internal peripheral i/o interrupt enabled b3 or b11 data bus b5-7 or b13-15 read 3 ireq read-only circuit ilevel (levels 0-7) group interrupt interrupt priority resolving circuit f/f clear to the cpu core set ei reset ivect read imask write figure 5.2.2 configuration of the interrupt control register (level-recognized type) 5 5-11 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.3 interrupt request sources in internal peripheral i/o the interrupt controller receives as inputs the interrupt requests from mjt (multijunction timer), dmac, serial i/o, a-d converter, rtd and can. for details about these interrupts, see each section in which the relevant internal peripheral i/o is described. table 5.3.1 interrupt request sources in internal peripheral i/o interrupt request sources contents number of icu type of input input sources source ( note 1) a-d0 conversion interrupt request a-d0 converter?s scan mode one-shot operation, 1 edge-recognized single mode or comparate mode completed sio0 transmit interrupt request sio0 transmission-completed or transmit buffer empty interrupt 1 edge-recognized sio0 receive interrupt request sio0 reception-completed or receive error interrupt 1 edge-recognized sio1 transmit interrupt request sio1 transmission-completed or transmit buffer empty interrupt 1 edge-recognized sio1 receive interrupt request sio1 reception-completed or receive error interrupt 1 edge-recognized sio2,3 transmit/receive interrupt sio2,3 reception-completed or receive error interrupt, 4 level-recognized request transmission-completed or transmit buffer empty interrupt rtd interrupt request rtd interrupt generation command 1 edge-recognized dma transfer interrupt request 0 dma0?4 transfer completed 5 level-recognized dma transfer interrupt request 1 dma5?9 transfer completed 5 level-recognized can0 transmit/receive & error can0 transmission or reception completed, can0 errorpassive, 35 level-recognized interrupt request can0 error bus-off, can0 bus error, can0 single shot can1 transmit/receive & error can1 transmission or reception completed, can1 error passive, 35 level-recognized interrupt request can1 error bus-off, can1 bus error, can1 single shot mjt output interrupt request 7 mjt output interrupt rgroup 7 (tms0, tms1 output) 2 level-recognized mjt output interrupt request 6 mjt output interrupt rgroup 6 (top8, top9 output) 2 level-recognized mjt output interrupt request 5 mjt output interrupt rgroup 5 (top10 output) 1 edge-recognized mjt output interrupt request 4 mjt output interrupt rgroup 4 (tio4?tio7 outputs) 4 level-recognized mjt output interrupt request 3 mjt output interrupt rgroup 3 (tio8, tio9 outputs) 2 level-recognized mjt output interrupt request 2 mjt output interrupt rgroup 2 (top0?top5 outputs) 6 level-recognized mjt output interrupt request 1 mjt output interrupt rgroup 1 (top6,top7 outputs) 2 level-recognized mjt output interrupt request 0 mjt output interrupt rgroup 0 (tio0?tio3 outputs) 4 level-recognized mjt input interrupt request 4 mjt input interrupt group 4 (tin3 input) 1 level-recognized mjt input interrupt request 3 mjt input interrupt group 3 (tin20?tin23 inputs) 4 level-recognized mjt input interrupt request 2 mjt input interrupt group 2 (tin16?tin19 inputs) 4 level-recognized mjt input interrupt request 1 mjt input interrupt group 1 (tin0 input) 1 level-recognized note 1: icu type of input source ? edge-recognized: interrupt requests are generated on a falling edge of the interrupt signal supplied to the icu. ? level-recognized: interrupt requests are generated when the interrupt signal supplied to the icu is held low. for this type of interrupt, the icu?s interrupt control register irq bit cannot be set or cleared in software. 5.3 interrupt request sources in internal peripheral i/o 5 5-12 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.4 icu vector table 5.4 icu vector table the icu vector table is used to set the start addresses of interrupt handlers for each internal peripheral i/o. the 23-source interrupt requests are assigned the following vector table addresses. table 5.4.1 icu vector table addresses interrupt request source icu vector table addresses mjt input interrupt request 4 (tin3 input) h'0000 0094 ? h'0000 0097 mjt input interrupt request 3 (tin20?23 input) h'0000 0098 ? h'0000 009b mjt input interrupt request 2 (tin16?19 input) h'0000 009c ? h'0000 009f mjt input interrupt request 1 (tin0 input) h'0000 00a0 ? h'0000 00a3 mjt output interrupt request 7 (tms0,1 output) h'0000 00a8 ? h'0000 00ab mjt output interrupt request 6 (top8,9 output) h'0000 00ac ? h'0000 00af mjt output interrupt request 5 (top10 output) h'0000 00b0 ? h'0000 00b3 mjt output interrupt request 4 (tio4?7 output) h'0000 00b4 ? h'0000 00b7 mjt output interrupt request 3 (tio8,9 output) h'0000 00b8 ? h'0000 00bb mjt output interrupt request 2 (top0?5 output) h'0000 00bc ? h'0000 00bf mjt output interrupt request 1 (top6,7 output) h'0000 00c0 ? h'0000 00c3 mjt output interrupt request 0 (tio0?3 output) h'0000 00c4 ? h'0000 00c7 dma0?4 interrupt request h'0000 00c8 ? h'0000 00cb sio1 receive interrupt request h'0000 00cc ? h'0000 00cf sio1 transmit interrupt request h'0000 00d0 ? h'0000 00d3 sio0 receive interrupt request h'0000 00d4 ? h'0000 00d7 sio0 transmit interrupt request h'0000 00d8 ? h'0000 00db a-d0 conversion interrupt request h'0000 00dc ? h'0000 00df dma5?9 interrupt request h'0000 00e8 ? h'0000 00eb sio2,3 transmit/receive interrupt request h'0000 00ec ? h'0000 00ef rtd interrupt request h'0000 00f0 ? h'0000 00f3 can0 transmit/receive & error interrupt request h'0000 010c ? h'0000 010f can1 transmit/receive & error interrupt request h'0000 0110 ? h'0000 0113 5 5-13 interrupt controller (icu) 32176 group user?s manual (rev.1.01) figure 5.5.1 example of priority resolution when accepting interrupt requests 5.5 description of interrupt operation 5.5.1 acceptance of internal peripheral i/o interrupts an interrupt request from any internal peripheral i/o is checked to see whether or not to accept by comparing its ilevel value set in the interrupt control register and the imask value of the interrupt request mask register. if its priority is higher than the imask value, the interrupt request is accepted. however, if two or more interrupt requests occur simultaneously, the interrupt controller resolves priority between these interrupt requests follow- ing the procedure described below. 1) the ilevel values set in the interrupt control registers for the respective internal peripheral i/os are compared with each other. 2) if the ilevel values are the same, priorities are resolved according to the predetermined hardware priority. 3) the ilevel and imask values are compared. if two or more interrupt requests occur simultaneously, the interrupt controller first compares their priority levels set in each interrupt control register?s ilevel bit to select an interrupt request that has the highest priority. if the interrupt requests have the same ilevel value, their priorities are resolved according to the hardware fixed priority. the interrupt request thus selected has its ilevel value compared with the imask value and if its priority is higher than the imask value, the interrupt controller sends an ei request to the cpu. interrupt requests may be masked by setting the interrupt request mask register and the interrupt control register?s ilevel bit (disabled at level 7) provided for each internal peripheral i/o and the psw register ie bit. 5.5 description of interrupt operation interrupt requested or not resolve priority according to interrupt priority level (ilevel) resolve priority according to hardware priority compare with imask value mjt input interrupt request 4 mjt output interrupt request 3 mjt output interrupt request 2 mjt output interrupt request 1 dma0-4 interrupt request a -d0 conversion interrupt request (ilevel settings) level 3 level 4 level 5 level 3 level 1 level 3 not requested requested requested requested requested requested hardware fixed priority accept interrupt if psw register ie bit = 1 level 3 level 3 level 3 can be accepted when imask = 4-7 1) 2) 3) 5 5-14 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.5 description of interrupt operation table 5.5.1 hardware fixed priority levels priority interrupt request source icu vector table address icu type of input source high mjt input interrupt request 4 (tin3 input) h'0000 0094 ? h'0000 0097 level-recognized mjt input interrupt request 3 (tin20?23 input) h'0000 0098 ? h'0000 009b level-recognized mjt input interrupt request 2 (tin16?19 input) h'0000 009c ? h'0000 009f level-recognized mjt input interrupt request 1 (tin0 input) h'0000 00a0 ? h'0000 00a3 level-recognized mjt output interrupt request 7 (tms0,1 output) h'0000 00a8 ? h'0000 00ab level-recognized mjt output interrupt request 6 (top8,9 output) h'0000 00ac ? h'0000 00af level-recognized mjt output interrupt request 5 (top10 output) h'0000 00b0 ? h'0000 00b3 edge-recognized mjt output interrupt request 4 (tio4?7 output) h'0000 00b4 ? h'0000 00b7 level-recognized mjt output interrupt request 3 (tio8,9 output) h'0000 00b8 ? h'0000 00bb level-recognized mjt output interrupt request 2 (top0?5 output) h'0000 00bc ? h'0000 00bf level-recognized mjt output interrupt request 1 (top6,7 output) h'0000 00c0 ? h'0000 00c3 level-recognized mjt output interrupt request 0 (tio0?3 output) h'0000 00c4 ? h'0000 00c7 level-recognized dma0?4 interrupt request h'0000 00c8 ? h'0000 00cb level-recognized sio1 receive interrupt request h'0000 00cc ? h'0000 00cf edge-recognized sio1 transmit interrupt request h'0000 00d0 ? h'0000 00d3 edge-recognized sio0 receive interrupt request h'0000 00d4 ? h'0000 00d7 edge-recognized sio0 transmit interrupt request h'0000 00d8 ? h'0000 00db edge-recognized a-d0 conversion interrupt request h'0000 00dc ? h'0000 00df edge-recognized dma5?9 interrupt request h'0000 00e8 ? h'0000 00eb level-recognized sio2,3 transmit/receive interrupt request h'0000 00ec ? h'0000 00ef level-recognized rtd interrupt request h'0000 00f0 ? h'0000 00f3 edge-recognized can0 transmit/receive & error interrupt h'0000 010c ? h'0000 010f level-recognized request can1 transmit/receive & error interrupt h'0000 0110 ? h'0000 0113 level-recognized low request table 5.5.2 ilevel settings and accepted imask values ilevel values set imask values at which interrupts are accepted 0 (ilevel = "000") accepted when imask is 1?7 1 (ilevel = "001") accepted when imask is 2?7 2 (ilevel = "010") accepted when imask is 3?7 3 (ilevel = "011") accepted when imask is 4?7 4 (ilevel = "100") accepted when imask is 5?7 5 (ilevel = "101") accepted when imask is 6?7 6 (ilevel = "110") accepted when imask is 7 7 (ilevel = "111") not accepted (interrupts disabled) 5 5-15 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.5.2 processing by internal peripheral i/o interrupt handlers (1) branching to the interrupt handler upon accepting an interrupt request, the cpu branches to the eit vector entry after performing the hardware preprocessing as described in section 4.3, ?eit processing procedure.? the eit vector entry for external interrupt (ei) is located at the address h?0000 0080. this address is where the instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is written. (2) processing in the external interrupt (ei) handler a typical operation of the external interrupt (ei) handler (for interrupts from internal peripheral i/o) is shown in figure 5.5.2. [1] saving each register to the stack save the bpc, psw and general-purpose registers to the stack. also, save the accumulator as neces- sary. [2] reading the interrupt request mask register (imask) and saving to the stack read the interrupt request mask register and save its content to the stack. [3] reading the interrupt vector register (ivect) read the interrupt vector register. this register holds the 16 low-order address bits of the icu vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. when the interrupt vector register is read, the following processing is automatically performed in hardware: ? the interrupt priority level of the accepted interrupt request (ilevel) is set in the imask register as a new imask value. (interrupts with lower priority levels than that of the accepted interrupt request source are masked.) ? the accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). ? the interrupt request (ei) to the cpu core is dropped. ? the icu?s internal sequencer is activated to start internal processing (interrupt priority resolution). [4] reading and overwriting the interrupt request mask register (imask) read the interrupt request mask register and overwrite it with the read value. this write to the imask register causes the following processing to be automatically performed in hardware: ? the interrupt request (ei) to the cpu core is dropped. ? the icu?s internal sequencer is activated to start internal processing (interrupt priority resolution). note: ? processing in [4] here is unnecessary when multiple interrupts are to be enabled in [6] below. [5] reading the icu vector table read the icu vector table for the accepted interrupt request source. the relevant icu vector table address can be obtained by zero-extending the content of the interrupt vector register that was read in [3] (i.e., the 16 low-order address bits of the icu vector table for the accepted interrupt request source). the icu vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) [6] enabling multiple interrupts to enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling multiple interrupts), set the psw register ie bit to "1". [7] branching to the internal peripheral i/o interrupt handler branch to the start address of the interrupt handler that was read out in [5]. [8] processing in the internal peripheral i/o interrupt handler [9] disabling interrupts clear the psw register ie bit to "0" to disable interrupts. 5.5 description of interrupt operation 5 5-16 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.5 description of interrupt operation [10] restoring the interrupt request mask register (imask) restore the interrupt request mask register that was saved to the stack in [2]. [11] restoring registers from the stack restore the registers that were saved to the stack in [1]. [12] completion of external interrupt processing execute the rte instruction to complete the external interrupt processing. the program returns to the state in which it was before the currently processed interrupt request was accepted. (3) identifying the source of the interrupt request generated if any internal peripheral i/o has two or more interrupt request sources, check the interrupt request status register provided for each internal peripheral i/o to identify the source of the interrupt request generated. (4) enabling multiple interrupts to enable multiple interrupts in the interrupt handler, set the psw register ie (interrupt enable) bit to enable interrupt requests to be accepted. however, before writing "1" to the ie bit, be sure to save each register (bpc, psw, general-purpose registers and imask) to the stack. note: ? before enabling multiple interrupts, read the interrupt vector register (ivect) and then the icu vector table, as shown in figure 5.5.2, ?typical handler operation for interrupts from internal peripheral i/o.? 5 5-17 interrupt controller (icu) 32176 group user?s manual (rev.1.01) figure 5.5.2 typical handler operation for interrupts from internal peripheral i/o 5.5 description of interrupt operation note 1: for operations at eit acceptance and return from eit, also see section 4.3, "eit processing procedure." note 2: do not read the interrupt vector register (ivect) or write to the interrupt request mask register (imask) in the eit handler unless interrupts are disabled (psw register ie bit = 0). note 3: when multiple interrupts are disabled, execute processing in [4]. processing in [4] is unnecessary if multiple interrupts are enabled by executing processing in [6] and [9]. note 4: to enable multiple interrupts, execute processing in [6] and [9]. note 5: to reenable interrupts (by setting the ie bit to 1) after reading the interrupt vector register (ivect), perform a dummy access to the internal memory, etc. before reenabling interrupts. in the example here, there is no need to add a dummy access because the icu vector table is read after reading the ivect register. similarly, to reenable interrupts (by setting the ie bit to 1) after writing to the interrupt request mask register (imask), perform a dummy access to the internal memory, etc. before reenabling interrupts. h'0000 0080 bra instruction read interrupt vector register (ivect) read icu vector table branch to the interrupt handler for each internal peripheral i/o rte h'0080 0004 h'0000 0094 h'0000 0113 interrupt handler ei (external interrupt) handler ei (external interrupt) vector entry interrupt handler start address program being executed interrupt generated ivect save bpc to the stack save psw to the stack save general-purpose registers to the stack restore bpc from the stack restore psw from the stack restore general-purpose registers from the stack read and save interrupt request mask register (imask) to the stack imask h'0080 0000 set psw register ie bit to 1 clear psw register ie bit to 0 restore interrupt request mask register (imask) from the stack [1] [2] [3] [5] [7] [8] [9] [6] [10] [11] icu vector table (note 1) (note 1) hardware preprocessing when eit is accepted hardware postprocessing when rte instruction is executed read and overwrite interrupt request mask register (imask) [4] [12] (note 2) (note 2) (note 3) (note 4) (note 5) (note 4) (note 2) interrupt handler [1] to [12]: processing of ei by interrupt handler 5 5-18 interrupt controller (icu) 32176 group user?s manual (rev.1.01) 5.6 description of system break interrupt (sbi) operation 5.6.1 acceptance of sbi system break interrupt (sbi) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. the system break interrupt is accepted anytime upon detec- tion of a falling edge on the sbi# signal input pin no matter how the psw register ie bit is set, and cannot be masked. 5.6.2 sbi processing by handler when the system break interrupt generated has been serviced, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. 5.6 description of system break interrupt (sbi) operation figure 5.6.1 typical sbi operation h'0000 0010 bra instruction sbi (system break interrupt) handler sbi (system break interrupt) vector entry program being executed sbi generated processing to shut down the system (note 1) note 1: do not return to the program that was being executed when the interrupt occurred. shut down or reset the system chapter 6 internal memory 6.1 outline of the internal memory 6.2 internal ram 6.3 internal flash memory 6.4 registers associated with the internal flash memory 6.5 programming the internal flash memory 6.6 virtual flash emulation function 6.7 connecting to a serial programmer (csio mode) 6.8 internal flash memory protect function 6.9 precautions to be taken when rewriting the internal flash memory 6 6-2 internal memory 32176 group user?s manual (rev.1.01) 6.1 outline of the internal memory the 32176 internally contains the following types of memory: ? 24-kbyte ram ? 512-kbytes, 384-kbytes or 256-kbytes flash memory 6.2 internal ram specifications of the internal ram are shown below. table 6.2.1 specifications of the internal ram item specification size 24 kbytes location address h?0080 4000 to h?0080 9fff wait insertion operates with zero wait states internal bus connection connected by 32-bit bus dual port by using the real-time debugger (rtd), data can be read (monitored) or written to any area of the internal ram via serial communication from external devices independently of the cpu. (see chapter 14, ?real-time debugger.?) notes: ? immediately after power-on reset (for the power-on case in which vdde also goes up from gnd), the value of the ram is undefined. ? if the ram is reset during ram backup (power for only vdde is on), the ram retains the value it had immediately before being reset. 6.3 internal flash memory specifications of the internal flash memory are shown below. table 6.3.1 specifications of the internal flash memory item specification size m32176f4: 512 kbytes m32176f3: 384 kbytes m32176f2: 256 kbytes location address m32176f4: h?0000 0000 to h?0007 ffff m32176f3: h?0000 0000 to h?0005 ffff m32176f2: h?0000 0000 to h?0003 ffff wait insertion operates with zero wait state durability standard product : 100 times 10000 (10k) times rewritable : 4-kbyte block (note 2) : 10,000 (10k) times -product (note 1) : other blocks : 1,000 (1k) times internal bus connection connected by 32-bit bus other virtual flash emulation function is incorporated. (see section 6.6, ?virtual flash emulation function.?) 6.1 outline of the internal memory note 1: the 10000 (10k) times rewritable product is offered as an optional item. for details about it, please contact your nearest office of renesas or its distributor. note 2: block 1: h?0000 2000 to h?0000 2fff block 2: h?0000 3000 to h?0000 3fff 6 6-3 internal memory 32176 group user?s manual (rev.1.01) figure 6.3.1 block configuration of the m32176f4?s internal flash memory 6.3 internal flash memory h'0002 0000 8kb 8kb 32kb 64kb h'0000 7fff h'0000 8000 h'0001 ffff h'0000 5fff h'0000 ffff h'0001 0000 h'0000 4000 h'0000 6000 64kb h'0002 ffff 64kb 64kb 64kb 64kb 64kb h'0003 0000 h'0003 ffff h'0004 0000 h'0004 ffff h'0005 0000 h'0005 ffff h'0006 0000 h'0006 ffff h'0007 0000 h'0007 ffff h'0000 0000 h'0000 1fff 8kb 4kb 4kb h'0000 2000 h'0000 2fff h'0000 3000 h'0000 3fff block 0 internal flash memory area of the m32176f4 (512 kbytes) unequal blocks equal blocks block 2 block 1 block 12 block 11 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 6 6-4 internal memory 32176 group user?s manual (rev.1.01) figure 6.3.2 block configuration of the m32176f3?s internal flash memory h'0002 0000 8kb 8kb 32kb 64kb h'0000 7fff h'0000 8000 h'0001 ffff h'0000 5fff h'0000 ffff h'0001 0000 h'0000 4000 h'0000 6000 64kb h'0002 ffff 64kb 64kb 64kb h'0003 0000 h'0003 ffff h'0004 0000 h'0004 ffff h'0005 0000 h'0005 ffff h'0000 0000 h'0000 1fff 8kb 4kb 4kb h'0000 2000 h'0000 2fff h'0000 3000 h'0000 3fff block 0 internal flash memory area of the m32176f3 (384 kbytes) unequal blocks equal blocks block 2 block 1 block 10 block 9 block 8 block 7 block 6 block 5 block 4 block 3 6.3 internal flash memory 6 6-5 internal memory 32176 group user?s manual (rev.1.01) figure 6.3.3 block configuration of the m32176f2?s internal flash memory h'0002 0000 8kb 8kb 32kb 64kb h'0000 7fff h'0000 8000 h'0001 ffff h'0000 5fff h'0000 ffff h'0001 0000 h'0000 4000 h'0000 6000 64kb h'0002 ffff 64kb h'0003 0000 h'0003 ffff h'0000 0000 h'0000 1fff 8kb 4kb 4kb h'0000 2000 h'0000 2fff h'0000 3000 h'0000 3fff block 0 internal flash memory area of the m32176f2 (256 kbytes) unequal blocks equal blocks block 2 block 1 block 8 block 7 block 6 block 5 block 4 block 3 6.3 internal flash memory 6 6-6 internal memory 32176 group user?s manual (rev.1.01) 6.4 registers associated with the internal flash memory 6.4 registers associated with the internal flash memory a register map associated with the internal flash memory is shown below. internal flash memory related register map address +0 address +1 address see pages b0 b7 b8 b15 h'0080 07e0 flash mode register flash status register 6-7 (fmod) (fstat) 6-8 h'0080 07e2 flash control register 1 flash control register 2 6-9 (fcnt1) (fcnt2) 6-10 h'0080 07e4 flash control register 3 flash control register 4 6-11 (fcnt3) (fcnt4) 6-13 h'0080 07e6 (use inhibited area) h'0080 07e8 virtual flash l bank register 0 6-15 (felbank0) h'0080 07ea virtual flash l bank register 1 6-15 (felbank1) (use inhibited area) h'0080 07f0 virtual flash s bank register 0 6-16 (fesbank0) h'0080 07f2 virtual flash s bank register 1 6-16 (fesbank1) | 6 6-7 internal memory 32176 group user?s manual (rev.1.01) 6.4.1 flash mode register flash mode register (fmod) 6 6-8 internal memory 32176 group user?s manual (rev.1.01) 6.4 registers associated with the internal flash memory 6.4.2 flash status register flash status register (fstat) 6 6-9 internal memory 32176 group user?s manual (rev.1.01) 6.4 registers associated with the internal flash memory 6.4.3 flash control registers flash control register 1 (fcnt1) 6 6-10 internal memory 32176 group user?s manual (rev.1.01) 6.4 registers associated with the internal flash memory flash control register 2 (fcnt2) 6 6-11 internal memory 32176 group user?s manual (rev.1.01) fprot = 0 fentry = 1 yes no fentry = 1 fprot = 1 fprot is not set to 1 if a write cycle to any other area occurs during this time. fpro t = 0 fpro t = 1 figure 6.4.1 protection unlocking flow flash control register 3 (fcnt3) 6 6-12 internal memory 32176 group user?s manual (rev.1.01) 6.4 registers associated with the internal flash memory (2) fpbsyck (prebusy check) bit (bit 7) the fpbsyck bit is used to check whether a 2-cycle command (confirmation command h?d0d0 or a com- mand that requires write data) issued to the flash memory during flash e/w enable mode has been accepted normally. if the fpbsyck bit is found to be "0" after issuing a command in the first cycle, it means that the command in the first cycle has been accepted normally. conversely, if the fpbsyck bit is found to be "1", it means that the command in the first cycle has not been accepted normally. in addition to the above, the fpbsyck bit is set to "1" in the following cases: 1) when in a ready state (fbusy = high after a command in the second cycle has been accepted) 2) when the clear status register command is issued 3) when the freset bit = "1" 4) when input on reset# pin is pulled low end check fstat for program error start write a first-cycle command fbusy = "1" time out ? yes no processing forcibly terminated yes no fpbsyck = "0" yes write a second-cycle command or data operation starts fbsyck = "0" yes write the clear status register command h'5050 no no figure 6.4.2 method to confirm the command acceptance by checking fcnt3 6 6-13 internal memory 32176 group user?s manual (rev.1.01) b8 9 1011121314b15 flockst freset 00000000 flash control register 4 (fcnt4) 6 6-14 internal memory 32176 group user?s manual (rev.1.01) figure 6.4.3 example of freset bit 1 (initializing flash status register 2) 6.4 registers associated with the internal flash memory figure 6.4.4 example of freset bit 2 (forcibly terminating programming/erasing operation) yes no 10s wait (by hardware timer or software timer) fmod register faens = 1? yes no freset = 1 fentry = 1 program/erase the flash memory error found freset = 0 program/erase the flash memory fentry = 0 programming/erase operation terminated normally yes no freset = 1 freset = 0 forcibly terminate flash programming/erase operation has timed ou t 10s wait (by hardware timer or software timer) fmod register faens = 1? 6 6-15 internal memory 32176 group user?s manual (rev.1.01) 6.4.4 virtual flash l bank registers virtual flash l bank register 0 (felbank0) 6 6-16 internal memory 32176 group user?s manual (rev.1.01) 6.4.5 virtual flash s bank registers virtual flash s bank register 0 (fesbank0) 6 6-17 internal memory 32176 group user?s manual (rev.1.01) 6.5 programming the internal flash memory 6.5 programming the internal flash memory 6.5.1 outline of internal flash memory programming to program or erase the internal flash memory, there are following two methods to choose depending on the situation: (1) when the flash write/erase program does not exist in the internal flash memory (2) when the flash write/erase program already exists in the internal flash memory for (1), set the fp pin = "high", mod0 = "high" and mod1 = "low" to enter boot mode. in this case, the cpu starts running the boot program immediately after reset. the boot program transfers the flash write/erase program into the internal ram. after the transfer, jump to a location in the ram and use the ram-resident program to set the flash control register 1 (fcnt1) fentry bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in boot mode + flash e/w enable mode). when the above is done, use the flash write/erase program that has been transferred into the internal ram to program or erase the internal flash memory. for (2), set the fp pin = "high", mod0 = "low" and mod1 = "low" to enter single-chip mode. transfer the flash write/erase program from the internal flash memory in which it has been prepared into the internal ram. after the transfer, jump to the ram and use the program transferred into the ram to set the flash control register 1 (fcnt1) fentry bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in single-chip mode + flash e/w enable mode). when the above is done, use the flash write/erase program that has been transferred into the internal ram to program or erase the internal flash memory. or flash e/w enable mode can be entered from external extension mode by setting the fp pin = "high", mod0 = "low" and mod1 = "high". during flash e/w enable mode (fp pin = 1, fentry = 1), the eit vector entry for external interrupt (ei) is relocated to the start address (h?0080 4000) of the internal ram. during normal mode, it is located in the flash area (h?0000 0080). to use an external interrupt (ei) in flash e/w enable mode, write at the beginning of the internal ram an instruc- tion for branching to the external interrupt (ei) handler that has been transferred into the internal ram. further- more, because the ivect register which is read out in the external interrupt (ei) handler has stored in it the flash memory address of the icu vector table, make sure the icu vector table to be used during flash e/w enable mode is prepared in the internal ram so that the value of the ivect register will be converted into the internal ram address of the icu vector table (for example, by adding an offset) before performing branch processing. 6 6-18 internal memory 32176 group user?s manual (rev.1.01) ei vector entry (h'0000 0080) internal rom area internal ram h'0000 0000 h'00ff ffff h'0080 4000 internal rom area internal ram h'0080 3fff flash e/w enable mode (fentry = 1) normal mode (fentry = 0) h'0000 0000 h'0080 3fff ei vector entry (h'0080 4000) h'0080 4000 h'00ff ffff figure 6.5.1 ei vector entry during flash e/w enable mode 6.5 programming the internal flash memory 6 6-19 internal memory 32176 group user?s manual (rev.1.01) figure 6.5.2 procedure for programming/erasing the internal flash memory (when the flash write/erase program does not exist in it) (1) when the flash write/erase program does not exist in the internal flash memory in this case, the boot program is used to program or erase the internal flash memory. to transfer the write data, use serial i/o1 in clock-synchronized serial mode. to program or erase the internal flash memory using a flash programmer, follow the procedure described below. sio1 cpu sio1 cpu flash write/ erase program mod1 = l sio1 cpu ram flash memory fp = l or h ram ram 6 6-20 internal memory 32176 group user?s manual (rev.1.01) reset# pin mod0 pin fentry bit fp pin mod1 pin power on mode selected reset signal deasserted (boot program starts) mode selected reset signal deasserted flash programming/erasing by the boot program settings by the boot program figure 6.5.3 internal flash memory write/erase timing (when the flash write/erase program does not exist in it) 6.5 programming the internal flash memory 6 6-21 internal memory 32176 group user?s manual (rev.1.01) figure 6.5.4 procedure for programming/erasing the internal flash memory (when the flash write/erase program already exists in it) (2) when the flash write/erase program already exists in the internal flash memory in this case, the flash write/erase program prepared in the internal flash memory is used to program or erase the internal flash memory. for programming/erase operation here, use the internal peripheral circuits in the manner suitable for the programming system. (all resources of the internal peripheral circuits such as the data bus, serial i/o and ports can be used.) the following shows an example for programming or erasing the internal flash memory by using serial i/o0 in single-chip mode. sio0 cpu flash write/ erase program sio0 cpu flash write/ erase program mod1 = l sio0 cpu ram flash write/ erase program fp = l or h write data ram ram 6 6-22 internal memory 32176 group user?s manual (rev.1.01) reset# pin mod0 pin fentry bit fp pin high or low high or low (single-chip or external extension) mod1 pin low high or low flash programming/erasing by the flash write/erase program flash rewrite starts flash mode turned on flash mode turned off flash write/erase program transferred into the ram figure 6 .5.5 internal flash memory write/erase timing (when the flash write/erase program already exists in it) 6.5 programming the internal flash memory 6 6-23 internal memory 32176 group user?s manual (rev.1.01) 6.5.2 controlling operation modes during flash programming the microcomputer?s operation mode is set by mod0, mod1 and flash control register 1 (fcnt1) fentry bit. the table below lists operation modes that may be used when programming or erasing the internal flash memory. table 6.5.1 operation modes set during flash programming/erase fp mod0 mod1 fentry (note 1) operation mode reset vector entry ei vector entry 0 0 0 0 single-chip mode start address of internal flash area 1 0 0 0 flash memory (h'0000 0080) (h'0000 0000) 0 1 0 0 processor mode start address of external external area area (h'0000 0000) (h'0000 0080) 0 0 1 0 external extension start address of internal flash area 1 0 1 0 mode flash memory (h'0000 0080) (h'0000 0000) 1 0 0 1 single-chip mode start address of internal beginning of internal ram + flash e/w enable flash memory (h'0080 4000) (h'0000 0000) 1 1 0 0 boot mode boot program startup flash area address (h'0000 0080) 1 1 0 1 boot mode + flash boot program startup beginning of internal ram e/w enable address (h'0080 4000) 1 0 1 1 external extension start address of internal beginning of internal ram mode + flash e/w flash memory (h'0080 4000) enable (h'0000 0000) ? 1 1 ? use inhibited ? ? note 1: indicates the flash control register 1 (fcnt1) fentry bit status (? denotes ?don?t care?). however, if fp = "0", writing "1" to fentry only results in it cleared to "0". note 2: always make sure the mod2 pin is connected low (= 0) to ground (gnd). 6.5 programming the internal flash memory 6 6-24 internal memory 32176 group user?s manual (rev.1.01) 6.5 programming the internal flash memory (1) flash e/w enable mode flash e/w enable mode is a mode in which the internal flash memory can be programmed or erased. in flash e/w enable mode, no programs can be executed in the internal flash memory. therefore, the necessary program must be transferred into the internal ram before entering flash e/w enable mode, so that it can be executed in the ram. (2) entering flash e/w enable mode flash e/w enable mode can only be entered when operating in single-chip, external extension or boot mode. furthermore, it is only when the fp pin = "high" and the flash control register 1 (fcnt1) fentry bit = "1" that flash e/w enable mode can be entered. flash e/w enable mode cannot be entered when operating in processor mode or the fp pin = "low". (3) detecting the mod0 and mod1 pin levels the mod0 and mod1 pin levels ("high" or "low") can be known by checking the p8 data register (port data register, h?0080 0708) mod0dt and mod1dt bits. p8 data register (p8data) 6 6-25 internal memory 32176 group user?s manual (rev.1.01) figure 6.5.6 procedure for entering flash e/w enable mode end start enter one of the following modes: single-chip mode boot mode external extension mode transfer the flash write/erase program into the internal ram set the flash control register in sfr area (fcnt1, h'0080 07e2) fentry bit to 0 set the flash control register in sfr area (fcnt1, h'0080 07e2) fentry bit to 1 execute flash write/erase command and various read commands (note 1) switched to the flash write/erase program wait for 1 s (using a hardware or software timer) jump to the flash memory or apply reset switched to normal mode check mod0/1 and fp pin levels ok no end fmod(h'0080 07e0) fpmod p8data(h'0080 0708) b0 = mod0dt b1 = mod1dt note 1: for details about each command, see section 6.5.3, "procedure for programming/erasing the internal flash memory." go to flash e/w enable mode 6.5 programming the internal flash memory 6 6-26 internal memory 32176 group user?s manual (rev.1.01) 6.5.3 procedure for programming/erasing the internal flash memory to program or erase the internal flash memory, set up chip mode to enter flash e/w enable mode and execute the flash write/erase program in the internal ram into which it has been transferred from the internal flash memory. in flash e/w enable mode, because the internal flash memory cannot be accessed for read as in normal mode, no programs present in it can be executed. therefore, the flash write/erase program must be made available in the internal ram before entering flash e/w enable mode. (once flash e/w enable mode is entered into, only flash command and no other commands can be used to access the internal flash memory.) to access the internal flash memory in flash e/w enable mode, issue commands for the internal flash memory address to be operated on. the table below lists the commands that can be issued in flash e/w enable mode. note: ? during flash e/w enable mode, the internal flash memory cannot be accessed for read or write wordwise. table 6.5.2 commands in flash e/w enable mode command name issued command data read array command h'ffff halfword program command h'4040 lock bit program command h'7777 block erase command h'2020 clear status register command h'5050 read lock bit status command h'7171 verify command (note 1) h'd0d0 note 1: ? this command must be issued immediately after the lock bit program, block erase or read lock bit status command. if the lock bit program, block erase or read lock bit status command is followed by other than the verify (h'd0d0) command, the lock bit program, block erase or read lock bit status command is not executed normally and terminated in error. (1) read array command writing the read array command (h?ffff) to any address of the internal flash memory places it in read mode. then read the desired flash memory address, and the content of that address will be read out. before exiting flash e/w enable mode, always be sure to execute the read array command. 6.5 programming the internal flash memory start write the read array command (h'ffff) to any address of the internal flash memory read the desired flash memory address end figure 6.5.7 read array 6 6-27 internal memory 32176 group user?s manual (rev.1.01) 6.5 programming the internal flash memory end confirm the result of execution of the programming process (note 1) last address? yes no start write the program data to the internal flash memory address to be programmed write the halfword program command (h'4040) to any address of the internal flash memory internal flash memory is programmed by halfword program wait for 1 s (using a hardware or software timer) fbusy bit = 1 time out? 600 s yes no forcibly terminated yes no to next halfword note 1: check flash status register (fstat) erase bit (for the erase status) and wrerr bit (for the write status). figure 6.5.8 halfword program (2) halfword program command the internal flash memory is programmed a halfword at a time, each halfword consisting of 2 bytes. to program the flash memory, write the program command (h?4040) to any address of the internal flash memory and then the program data to the address to be programmed. the protected flash memory blocks cannot be accessed for write by the halfword program command. halfword programming is automatically performed by the internal control circuit, and whether the halfword program command has finished can be known by checking the flash status register fbusy bit. (see section 6.4.2, ?flash status registers.?) while the fbusy bit = "0", the next programming cannot be per- formed. 6 6-28 internal memory 32176 group user?s manual (rev.1.01) 6.5 programming the internal flash memory (3) lock bit program command the internal flash memory can be protected against programming/erase operation one block at a time. the lock bit program command is provided for protecting the flash memory blocks. write the lock bit program command (h?7777) to any address of the internal flash memory. next, write the verify command (h?d0d0) to the last even address of the flash memory block to be protected, and this memory block is thereby protected against programming/erase operation. to remove protection, use the flash control register 2 (fcnt2) fprot bit to invalidate protection by a lock bit (see section 6.4.3, ?flash control registers?) and erase the flash memory block whose protection is to be removed. (the content of that memory block is also erased.) lock bit programming is automatically performed by the internal control circuit, and whether the lock bit program command has finished can be known by checking the flash status register (fstat) fbusy bit. (see section 6.4.2, ?flash status registers.?) while the fbusy bit = "0", the next programming cannot be performed. the table below lists the target flash memory blocks and their addresses to be specified when writing the verify command data. table 6.5.3 m32176f4 target blocks and specified addresses target block specified address 0 h'0000 1ffe 1 h'0000 2ffe 2 h'0000 3ffe 3 h'0000 5ffe 4 h'0000 7ffe 5 h'0000 fffe 6 h'0001 fffe 7 h'0002 fffe 8 h'0003 fffe 9 h'0004 fffe 10 h'0005 fffe 11 h'0006 fffe 12 h'0007 fffe table 6.5.4 m32176f3 target blocks and specified addresses target block specified address 0 h'0000 1ffe 1 h'0000 2ffe 2 h'0000 3ffe 3 h'0000 5ffe 4 h'0000 7ffe 5 h'0000 fffe 6 h'0001 fffe 7 h'0002 fffe 8 h'0003 fffe 9 h'0004 fffe 10 h'0005 fffe 6 6-29 internal memory 32176 group user?s manual (rev.1.01) end start write the verify command (h'd0d0) to the last even address of the flash memory block to be protected write the lock bit program command (h'7777) to any address of the internal flash memory lock bit is programmed by lock bit program wait for 1 s (using a hardware or software timer) fbusy bit = 1 time out? yes no forcibly terminated yes no confirm the result of execution of the programming process (note 1) note 1: check flash status register (fstat) erase bit (for the erase status) and wrerr bit (for the write status). 600 s figure 6.5.9 lock bit program 6.5 programming the internal flash memory table 6.5.5 m32176f2 target blocks and specified addresses target block specified address 0 h'0000 1ffe 1 h'0000 2ffe 2 h'0000 3ffe 3 h'0000 5ffe 4 h'0000 7ffe 5 h'0000 fffe 6 h'0001 fffe 7 h'0002 fffe 8 h'0003 fffe 6 6-30 internal memory 32176 group user?s manual (rev.1.01) end start write the verify command (h'd0d0) to the last even address of the flash memory block to be erased write the block erase command (h'2020) to any address of the internal flash memory internal flash memory contents are erased by the block erase command wait for 1 s (using a hardware or software timer) time out? yes no forcibly terminated yes no confirm the result of execution of the erase process (note 1) fbusy bit = 1 8 s note 1: check flash status register (fstat) erase bit (for the erase status) and wrerr bit (for the write status). figure 6.5.10 block erase 6.5 programming the internal flash memory (4) block erase command the block erase command erases the content of the internal flash memory one block at a time. to perform this operation, write the command data (h?2020) to any address of the internal flash memory. next, write the verify command (h?d0d0) to the last even address of the flash memory block to be erased (see tables 6.5.3, 6.5.4 and 6.5.5, ?m32176 target blocks and specified addresses?). the protected flash memory blocks cannot be erased by the block erase command. block erase operation is automatically performed by the internal control circuit, and whether the block erase command has finished can be known by checking the flash status register (fstat) fbusy bit. (see section 6.4.2, ?flash status registers.?) while the fbusy bit = "0", the next block erase operation cannot be performed. 6 6-31 internal memory 32176 group user?s manual (rev.1.01) 6.5 programming the internal flash memory (7) clear status register command the clear status register command clears the flash status register (fstat) erase (erase status), and wrerr (write status) bits to "0". write the command data (h?5050) to any address of the internal flash memory, and flash status register is thereby initialized. also, issue the clear status register command, and flash status register 3 (fcnt3) is initialized. if an error occurs when programming or erasing the flash memory and the flash status register (fstat) erase (erase status) or wrerr (write status) bit is set to "1", the next programming or erase operation cannot be executed unless each status bit is cleared to "0". start write the clear status register command (h'5050) to any address of the internal flash memory end figure 6.5.11 clear status register 6 6-32 internal memory 32176 group user?s manual (rev.1.01) b01234567891011121314b15 flbst ? ??????????????? 6.5 programming the internal flash memory start write the read lock bit status command (h'7171) to any address of the internal flash memory read the last even address of the flash memory block to be checked end figure 6.5.12 read lock bit status (memory area read mode) (8) read lock bit status command the read lock bit status command is provided for checking whether a flash memory block is protected against programming/erase operation. the method for reading lock bit can be chosen from the following depends on the setting for flash control register 2 (fcnt2) flocks (lock bit read mode select) bit. 1) memory area read mode (flocks bit = 0) write the command data (h?7171) to any address of the internal flash memory. next, read the last even address of the flash memory block to be checked (see tables 6.5.3, 6.5.4 and 6.5.5, ?m32176 target blocks and specified addresses?), and the read data shows whether the target block is protected. if the flbst (lock bit) in the read data is "0", it means that the target memory block is protected. if the flbst (lock bit) is "1", it means that the target memory block is not protected. lock bit status register (flbst) 6 6-33 internal memory 32176 group user?s manual (rev.1.01) 6.5 programming the internal flash memory 2) register read mode (flocks bit = 1) write the command data (h?7171) to any address of the target block. next, write the verify command data (h'd0d0), and the flash control register 4 (fcnt4) flockst (lock bit status) bit shows whether the target block is protected. end start write the verify command (h'd0d0) to any address of the block write the read lock bit status command (h'7171) to any address of the block to be read time out? yes no forcibly terminated yes no confirm the lock bit status bit (note 1) fbusy bit = 1 10 s note 1: check flash status register 4 (fstat4) flockst bit. figure 6.5.13 read lock bit status (register read mode) the following describes how to write to the lock bit. a) to clear the lock bit to "0" (flash protected) issue the lock bit program command (h?7777) to the memory block to be protected. b) to set the lock bit to "1" (flash unprotected) after setting the fprot bit in flash control register 2 to 1 (protection by lock bit disabled), use the block erase command (h?2020) to erase the memory block to be unprotected. the lock bit cannot be set to "1" directly by writing to it. c) lock bit status when reset because the lock bit is a nonvolatile bit, it remains unaffected when the microcomputer is reset or powered off. 6 6-34 internal memory 32176 group user?s manual (rev.1.01) 6.5.4 flash programming time (reference) the following shows the time needed to program internal flash memory for reference. (1) m32176f4 [1] time required for transfer by sio (for a transfer data size of 512 kb) 1/57,600 bps [2] time required for programming the flash memory 512 kb / 2-byte [3] time required for erasing the entire area 0.3 s [4] total flash programming time (entire 512 kb area) when communicating at 57,600 bps via uart, the flash programming time can be ignored because it is very short compared to the serial communication time. therefore, the total flash programming time can be calculated using the equation below. [1] + [3] = approx. 108 [s] if the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. [2] + [3] = approx. 15 [s] (1) m32176f3 1) time required for transfer by sio (for a transfer data size of 384 kb) 1/57,600 bps 2) time required for programming the flash memory 384 kb / 2-byte 3) time required for erasing the entire area 0.3 s 4) total flash programming time (entire 384 kb area) when communicating at 57,600 bps via uart, the flash programming time can be ignored because it is very short compared to the serial communication time. therefore, the total flash programming time can be calculated using the equation below. [1] + [3] = approx. 82 [s] if the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. [2] + [3] = approx. 11 [s] 6.5 programming the internal flash memory 6 6-35 internal memory 32176 group user?s manual (rev.1.01) 6.5 programming the internal flash memory (3) m32176f2 1) time required for transfer by sio (for a transfer data size of 256 kb) 1/57,600 bps 2) time required for programming the flash memory 256 kb / 2-byte 3) time required for erasing the entire area 0.3 s 4) total flash programming time (entire 256 kb area) when communicating at 57,600 bps via uart, the flash programming time can be ignored because it is very short compared to the serial communication time. therefore, the total flash programming time can be calculated using the equation below. [1] + [3] = approx. 55 [s] if the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. [2] + [3] = approx. 8 [s] 6 6-36 internal memory 32176 group user?s manual (rev.1.01) 6.6 virtual flash emulation function the microcomputer has the function to map 8-kbyte memory blocks of the internal ram (max. 2 blocks) into areas (l banks) of the internal flash memory that are divided in 8-kbyte units and to map 4-kbyte memory blocks of the internal ram (max. 2 blocks) into areas (s banks) of the internal flash memory that are divided in 4-kbyte units. this functions is referred to as the virtual flash emulation function. this function allows the data located in 4-kbyte or 8-kbyte blocks of the internal ram to be changed with the contents of internal flash memory at the addresses specified by the virtual flash bank register. that way, the relevant ram data can read out by reading the content of internal flash memory. for applications that require modifying the contents of internal flash memory (e.g., data table) during operation, this function enables dynamic data modification by modifying the relevant ram data. the ram blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual ram. this function, when used in combination with the microcomputer?s internal real-time debugger (rtd), allows the data table, etc. created in the internal flash memory to be referenced or rewritten from the outside, thereby facili- tating data table tuning from an external device. note: ? before programming/erasing the internal flash memory, always be sure to exit this virtual flash emulation mode. figure 6.6.1 internal ram bank configuration of the m32176 6.6 virtual flash emulation function ram bank l block 0 (felbank0) 8 kbytes h'0080 4000 h'0080 6000 h'0080 7000 ram bank s block 0 (fesbank0) 4 kbytes ram bank s block 1 (fesbank1) 4 kbytes h'0080 7fff ram bank l block 1 (felbank1) 8 kbytes h'0080 8000 h'0080 9fff 6 6-37 internal memory 32176 group user?s manual (rev.1.01) 6.6.1 virtual flash emulation area the following shows the internal flash memory areas in which the virtual flash emulation function is applicable. using the virtual flash l bank register (felbank0, felbank1), select one among all l banks of internal flash memory that are divided in 8-kbyte units (by setting the seven start address bits a12?a18 of the desired l bank in the virtual flash l bank register lbankad bits). then set the virtual flash l bank register?s flash emula- tion l enable bit (modenl) to "1", and the selected l bank area will be replaced with 8-kbyte blocks of the internal ram, up to two blocks in all. using the virtual flash s bank register (fesbank0, fesbank1), select one among all s banks of internal flash memory that are divided in 4-kbyte units (by setting the eight start address bits a12?a19 of the desired s bank in the virtual flash s bank register sbankad bits). then set the virtual flash s bank register?s flash emulation s enable bit (modens) to "1", and the selected s bank area will be replaced with 4-kbyte blocks of the internal ram, up to two blocks in all. two 8-kbyte units l banks and two 4-kbyte units s banks, total of four banks (maximum), can be selected. notes: ? if the same bank area is set in two or more virtual flash bank registers and each register?s flash emulation enable bit is enabled, the bank is assigned the corresponding internal ram area (8- kbyte or 4-kbyte) according to the priority given below. felbank0 > fesbank0 > fesbank1 > felbank1 ? during virtual flash emulation mode, ram can be accessed for read and write from the internal ram area and the virtual flash set area. ? before reading any virtual flash area after setting the flash control register 1 virtual flash emula- tion mode bit to "1", be sure that there must be an interval of at least three clocks (cpu clocks). ? before reading any virtual flash area after setting the virtual flash bank register (l bank and s bank registers) virtual flash emulation enable bit and bank address bits, be sure that there must be an interval of at least three clocks (cpu clocks). 6.6 virtual flash emulation function 6 6-38 internal memory 32176 group user?s manual (rev.1.01) 6.6 virtual flash emulation function figure 6.6.2 m32176f4 virtual flash emulation area divided in 8-kbyte units figure 6.6.3 m32176f4 virtual flash emulation area divided in 4-kbyte units h'0000 0000 h'0000 2000 h'0080 4000 h'0000 4000 h'0007 e000 h'0007 c000 h'0080 6000 h'0080 7000 h'0080 8000 8 kbytes 4 kbytes 4 kbytes 8 kbytes l bank 0 (8 kbytes) l bank 1 (8 kbytes) l bank 2 (8 kbytes) l bank 62 (8 kbytes) l bank 63 (8 kbytes) 6 6-39 internal memory 32176 group user?s manual (rev.1.01) 6.6 virtual flash emulation function figure 6.6.4 m32176f3 virtual flash emulation area divided in 8-kbyte units figure 6.6.5 m32176f3 virtual flash emulation area divided in 4-kbyte units h'0000 0000 h'0000 2000 h'0080 4000 h'0000 4000 h'0005 e000 h'0005 c000 h'0080 6000 h'0080 7000 h'0080 8000 8 kbytes 4 kbytes 4 kbytes 8 kbytes l bank 0 (8 kbytes) l bank 1 (8 kbytes) l bank 2 (8 kbytes) l bank 46 (8 kbytes) l bank 47 (8 kbytes) 6 6-40 internal memory 32176 group user?s manual (rev.1.01) figure 6.6.6 m32176f2 virtual flash emulation area divided in 8-kbyte units 6.6 virtual flash emulation function figure 6.6.7 m32176f2 virtual flash emulation area divided in 4-kbyte units h'0000 0000 h'0000 2000 h'0080 4000 h'0000 4000 h'0003 e000 h'0003 c000 h'0080 6000 h'0080 7000 h'0080 8000 8 kbytes 4 kbytes 4 kbytes 8 kbytes l bank 0 (8 kbytes) l bank 1 (8 kbytes) l bank 2 (8 kbytes) l bank 30 (8 kbytes) l bank 31 (8 kbytes) 6 6-41 internal memory 32176 group user?s manual (rev.1.01) figure 6.6.8 values set in the m32176f4?s virtual flash bank register when divided in 8-kbyte units figure 6.6.9 values set in the m32176f4?s virtual flash bank register when divided in 4-kbyte units h'0000 0000 l bank start address of bank in flash memory values set in l bank address (lbankad) bit l bank 0 l bank 1 l bank 2 l bank 62 l bank 63 h'0000 2000 h'0000 4000 h'0007 c000 h'0007 e000 h'00 h'02 h'04 h'7c h'7e (note 1) (note 1) (note 1) (note 1) (note 1) note 1: set the seven start address bits a12-a18 of each l bank of internal flash memory that is divided in 8-kbyte units in the virtual flash l bank register's l bank address (lbankad) bits. h'0000 0000 s bank s bank 0 s bank 1 s bank 2 s bank 126 s bank 127 h'0000 1000 h'0000 2000 h'0007 e000 h'0007 f000 h'00 h'01 h'02 h'7e h'7f start address of bank in flash memory values set in s bank address (sbankad) bit (note 1) (note 1) (note 1) (note 1) (note 1) note 1: set the eight start address bits a12-a19 of each s bank of internal flash memory that is divided in 4-kbyte units in the virtual flash s bank register's s bank address (sbankad) bits. 6.6 virtual flash emulation function 6 6-42 internal memory 32176 group user?s manual (rev.1.01) 6.6 virtual flash emulation function figure 6.6.10 values set in the m32176f3?s virtual flash bank register when divided in 8-kbyte units figure 6.6.11 values set in the m32176f3?s virtual flash bank register when divided in 4-kbyte units h'0000 0000 l bank l bank 0 l bank 1 l bank 2 l bank 46 l bank 47 h'0000 2000 h'0000 4000 h'0005 c000 h'0005 e000 h'00 h'02 h'04 h'5c h'5e start address of bank in flash memory values set in l bank address (lbankad) bit (note 1) (note 1) (note 1) (note 1) (note 1) note 1: set the seven start address bits a12-a18 of each l bank of internal flash memory that is divided in 8-kbyte units in the virtual flash l bank register's l bank address (lbankad) bits. h'0000 0000 s bank s bank 0 s bank 1 s bank 2 s bank 94 s bank 95 h'0000 1000 h'0000 2000 h'0005 e000 h'0005 f000 h'00 h'01 h'02 h'5e h'5f start address of bank in flash memory values set in s bank address (sbankad) bit (note 1) (note 1) (note 1) (note 1) (note 1) note 1: set the eight start address bits a12-a19 of each s bank of internal flash memory that is divided in 4-kbyte units in the virtual flash s bank register's s bank address (sbankad) bits. 6 6-43 internal memory 32176 group user?s manual (rev.1.01) 6.6 virtual flash emulation function figure 6.6.12 values set in the m32176f2?s virtual flash bank register when divided in 8-kbyte units figure 6.6.13 values set in the m32176f2?s virtual flash bank register when divided in 4-kbyte units h'0000 0000 l bank l bank 0 l bank 1 l bank 2 l bank 30 l bank 31 h'0000 2000 h'0000 4000 h'0003 c000 h'0003 e000 h'00 h'02 h'04 h'3c h'3e start address of bank in flash memory values set in l bank address (lbankad) bit (note 1) (note 1) (note 1) (note 1) (note 1) note 1: set the seven start address bits a12-a18 of each l bank of internal flash memory that is divided in 8-kbyte units in the virtual flash l bank register's l bank address (lbankad) bits. h'0000 0000 s bank s bank 0 s bank 1 s bank 2 s bank 62 s bank 63 h'0000 1000 h'0000 2000 h'0003 e000 h'0003 f000 h'00 h'01 h'02 h'3e h'3f start address of bank in flash memory values set in s bank address (sbankad) bit (note 1) (note 1) (note 1) (note 1) (note 1) note 1: set the eight start address bits a12-a19 of each s bank of internal flash memory that is divided in 4-kbyte units in the virtual flash s bank register's s bank address (sbankad) bits. 6 6-44 internal memory 32176 group user?s manual (rev.1.01) 6.6.2 entering virtual flash emulation mode to enter virtual flash emulation mode, set the flash control register 1 (fcnt1) femmod bit by writing "1". after entering virtual flash emulation mode, set the virtual flash bank register moden bit to "1" to enable the virtual flash emulation function. even during virtual flash emulation mode, the internal ram area (h?0080 4000 through h?0080 9fff) can be accessed the same way as in usual internal ram. figure 6.6.14 virtual flash emulation mode sequence 6.6 virtual flash emulation function set ram location address in virtual flash bank register lbankad address a12?a18 sbankad address a12?a19 write flash data to ram enable virtual flash emulation modenl 1 modens 1 settings completed enter virtual flash emulation mode femmod 1 settings start 6 6-45 internal memory 32176 group user?s manual (rev.1.01) 6.6.3 application example of virtual flash emulation mode by using two ram areas that have been set in the same flash area by the virtual flash emulation function, the data in the flash memory can be replaced successively. figure 6.6.15 application example of virtual flash emulation mode (1/2) replace area flash memory ram block 0 data write to ram0 ram block 1 (1) operation when reset replaced data write to ram1 (2) programming operation using ram block 0 flash memory initial value initial value ram block 0 ram block 1 replaced (3) programming operation switched from ram block 0 to ram block 1 flash memory initial value ram block 0 ram block 1 ram block 1 bank xx bank xx bank xx bank xx specified bank xx specified bank xx specified (settings invalid) ram block 0 ram block 0 6.6 virtual flash emulation function 6 6-46 internal memory 32176 group user?s manual (rev.1.01) replaced (4) programming operation using ram block 1 flash memory initial value ram block 0 ram block 1 ram block 1 bank xx bank xx specified replaced (5) programming operation switched from ram block 1 to ram block 0 ram block 0 flash memory initial value ram block 0 ram block 1 ram block 1 bank xx bank xx specified bank xx specified (settings invalid) (6) go to (2) note: enclosed in are the valid area. data write to ram0 figure 6.6.17 application example of virtual flash emulation mode (2/2) 6.6 virtual flash emulation function 6 6-47 internal memory 32176 group user?s manual (rev.1.01) 6.7 connecting to a serial programmer 6.7 connecting to a serial programmer (csio mode) for the internal flash memory to be rewritten in boot mode + flash e/w enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. table 6.7.1 processing microcomputer pins before using a serial programmer pin name pin no. sclki1 71 rxd1 70 txd1 69 p84 68 fp 94 mod0 92 mod1 93 mod2 123 reset# 91 xin 4 xo ut 5 sbi# 77 vref0 42 avcc0 43 avss0 60 vdd 108 vcce 20, 65, 95, 132 excvcc 61, 137 excvdd 73 excosc- vcc 6 vss 3, 21, 62, 72, 96, 138 jtrst 111 function transfer clock input serial data input (received data) serial data output (transmit data) transmit/receive enable output flash memory protect operation mode 0 operation mode 1 operation mode 2 reset clock input clock output sbi interrupt input remark pull high pull high pull high pull high connect to the main power supply connect to ground connect to ground after setting mod0/mod1, ground and back to main power supply pull high or low reference voltage input for a-d converter analog power supply analog ground ram backup power supply main power supply connects external capacitance for the internal power supply connects external capacitance for the ram power supply connects external capacitance for the oscillator power supply ground jtag reset input connect to the main power supply connect to the main power supply connect to ground connect to the main power supply 5 v +/- 10% or 3.3 v +/- 10% need to be grounded to earth via capacitor need to be grounded to earth via capacitor need to be grounded to earth via capacitor 0v pull low notes ? pin processing is not required for those that are not listed above. 6 6-48 internal memory 32176 group user?s manual (rev.1.01) 6.7 connecting to a serial programmer figure 6.7.1 pin connection diagram the diagram below shows an example of a user system configuration which has had a serial programmer con- nected. after the user system is powered on, the serial programmer writes to the internal flash memory in clock- synchronized serial mode. no communication problems associated with the oscillator frequency may occur. if the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. note that the serial programmer uses the ad- dresses h?0000 0084 through h?0000 0093 as an area in which to check the id for flash memory protection. if the internal flash memory needs to be protected, set any id in this area. 2k ? 32176 xout xin jtrst mod1 osc-vss avss0 vss reset# fp mod0 p84/sclki0/sclko0 p87/sclki1/sclko1 p86/rxd1 p85/txd1 excvdd excvcc vref0 avcc0 excosc-vcc vdde vcce connect to the vcce (5 or 3.3 v) power supply rail main power supply connect to the vcce (5 or 3.3v) power supply rail main power supply (for reference) rxd (input) txd (output) sclk0 (output) busy (input) mod0 (output) fp (output) reset (output) gnd (common) connector flash programmer signals to system circuit set microcomputer operating conditions user system board notes: turn on the power for the user system before writing to the internal flash memory. if p84-p87 are used in the system circuit, connection to a serial programmer must be taken into consideration. sbi# must be fixed high or low to ensure that no interrupts will be generated. the pullup resistance values of p84, p86 and p87 must be selected to suit the system design condition. the typical pullup resistance values of p84, p86 and p87 are 4.7 to 10 k ? . the status of any other ports that are not shown here will not affect flash memory programming. make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory. mod2 6 6-49 internal memory 32176 group user?s manual (rev.1.01) 6.8 internal flash memory protect function the internal flash memory has the following four types of protect functions to prevent it from being inadvertently rewritten or illegally copied, programmed or erased. (1) flash memory protect id when using a tool to program/erase the internal flash memory such as a general-purpose programmer or emu- lator, the id entered by a tool and the id stored in the internal flash memory are collated. unless the correct id is entered, no programming/erase operations can be performed. (for some tools, tool execution is enabled after erasing the entire flash memory area, and the internal flash memory becomes accessible for write.) (2) protection by fp pin the internal flash memory is protected in hardware against programming/erase operation by pulling the fp (flash protect) pin low. furthermore, because the fp pin level can be known by reading the flash mode regis- ter (fmod)?s fpmod (external fp pin status) bit in the flash write/erase program, the internal flash memory can also be protected in software. for systems that do not require protection by setting external pins, the fp pin may be fixed high to simplify the operation to program/erase the internal flash memory. (3) protection by fentry bit flash e/w enable mode cannot be entered into unless the flash control register 1 (fcnt1)?s fentry (flash mode entry) bit is set to "1". to set the fentry bit to "1", write "0" and then "1" in succession while the fp pin is high. (4) protection by a lock bit any block of internal flash memory can be protected by setting the lock bit provided for it to "0". that memory block is disabled against programming/erase operation. 6.8 internal flash memory protect function 6 6-50 internal memory 32176 group user?s manual (rev.1.01) 6.9 precautions to be taken when rewriting the internal flash memory 6.9 precautions to be taken when rewriting the internal flash memory the following describes precautions to be taken when programming/erasing the internal flash memory. ? when the internal flash memory is programmed or erased, a high voltage is generated internally. because mode transitions during programming/erase operation may cause the chip to break down, make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes. ? if the system uses any pins that are to be used by a general-purpose programming/erase tool, care must be taken to prevent adverse effects on the system when the tool is connected. ? if the internal flash memory needs to be protected while using a general-purpose programming/erase tool, set any id in the flash memory protect id verification area (h?0000 0084 to h?0000 0093). ? if the internal flash memory does not need to be protected while using a general-purpose programming/erase tool, fill the entire flash memory protect id verification area (h?0000 0084 to h?0000 0093) with h?ff. ? if the flash status register (fstat)?s each error status is to be cleared (initialized to h?80) by resetting the flash control register 4 (fcnt4) freset bit, check to see that the flash status register (fstat) fbusy bit = "1" (ready) before clearing the error status. ? before resetting the flash control register 1 (fcnt1) fentry bit from "1" to "0", check to see that the flash status register (fstat) fbusy bit = "1" (ready). ? do not clear the fentry bit if the flash control register 1 (fcnt1) fentry bit = "1" and the flash status register (fstat) fbusy bit = "0" (being programmed or erased). ? when programming/erasing via jtag, the flash memory can be programmed or erased regardless of the pin state because the fp pin is controlled internally within the chip. chapter 7 reset 7.1 outline of reset 7.2 reset operation 7.3 internal state immediately after exiting reset 7.4 things to be considered after exiting reset 7 7-2 reset 32176 group user?s manual (rev.1.01) 7.1 outline of reset the microcomputer is reset by applying a low-level signal to the reset# input pin. the microcomputer is gotten out of a reset state by releasing the reset# input back high, upon which the reset vector entry address is set in the program counter (pc) and the cpu starts executing from the reset vector entry. 7.2 reset operation when a low-level signal in width of more than 200 ns (a duration needed for noise cancellation) is applied to the reset# pin, the microcomputer enters a reset state. at this time, the internal circuits (including the cpu) are reset. (for details about the pin state when reset, see table 1.4.1, ?pin assignments?) when the reset# input is returned high, the internal circuits get out of a reset state 512-513 bclk periods after that. 7.1 outline of reset noise canceller s r ovf internal circuit reset signal flip-flop counter reset# extended for a duration during which the reset# input is held low 512?513bclk reset# pin reset signal (internal signal) past the noise canceller internal circuit reset signal (internal signal) duration needed for noise cancellation (note 1) 200ns note 1: if the low level duration of the reset signal is less than 200 ns, it is cancelled by the noise canceller. figure 7.2.2 reset sequence figure 7.2.1 reset circuit 7 7-3 reset 32176 group user?s manual (rev.1.01) 7.2 reset operation 7.2.1 reset at power-on when powering on the microcomputer, hold the reset# signal input pin low until the rated power supply volt- age is reached and the microcomputer?s internal x4 clock generator becomes oscillating stably. 7.2.2 reset during operation to reset the microcomputer during operation, hold the reset# signal input pin low for more than 200 ns. 7.2.3 reset vector relocation during flash programming when the microcomputer is reset after entering boot mode, the reset vector entry address is moved to the boot program startup address. the boot program starts running after the reset state is deasserted. for details, see section 6.5, ?programming the internal flash memory.? 7 7-4 reset 32176 group user?s manual (rev.1.01) 7.3 internal state immediately after exiting reset 7.3 internal state immediately after exiting reset the table below lists the internal state of the microcomputer immediately after it has gotten out of a reset state. for details about the initial register state of each internal peripheral i/o, see each section in this manual in which the relevant internal peripheral i/o is described. table 7.3.1 internal state immediately after exiting reset register state after reset psw (cr0) b'0000 0000 0000 0000 ??00 000? 0000 0000 (bsm, bie, bc bits = undefined) cbr (cr1) h'0000 0000 (c bits = 0) spi (cr2) undefined spu (cr3) undefined bpc (cr6) undefined pc h'0000 0000 (executed beginning with the address h?0000 0000) (note 1) r0?r15 undefined acc (accumulator) undefined ram undefined when reset at power-on. (however, if the ram is gotten out of reset after returning from backup mode, it retains the content it had before being reset.) note 1: when in boot mode, the cpu executes the boot program. 7.4 things to be considered after exiting reset ? input/output ports after exiting the reset state, the microcomputer?s input/output ports are disabled against input in order to prevent current from flowing through the port. to use any ports in input mode, set the port input special function control register (picnt) pien0 bit to enable them for input. for details, see section 8.3, ?input/output port related registers.? chapter 8 input/output ports and pin functions 8.1 outline of input/output ports 8.2 selecting pin functions 8.3 input/output port related registers 8.4 port input level switching function 8.5 port peripheral circuits 8.6 precautions on input/output ports 8 8-2 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.1 outline of input/output ports the 32176 has a total of 96 input/output ports from p0-p13, p15, p17 and p22 (except p5, which is reserved for future use). these input/output ports can be used as input or output ports by setting the respective direction registers. each input/output port is a dual-function or triple-function pin, sharing the pin with other internal peripheral i/o or external extension bus signal line. pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. (if any internal peripheral i/o has still another function, it is also necessary to set the register provided for that peripheral i/o.) the microcomputer also has a port input function enable bit that can be used to prevent current from flowing into the input ports. this helps to simplify the software and hardware processing to be performed immediately after reset or during flash programming. note that before any ports can be used in input mode, this port input function enable bit must be set accordingly. the input/output ports are outlined below. table 8.1.1 outline of input/output ports item specification number of ports total 96 ports p0 : p00?p07 (8 ports) p1 : p10?p17 (8 ports) p2 : p20?p27 (8 ports) p3 : p30?p37 (8 ports) p4 : p41?p47 (7 ports) p6 : p61?p63 (3 ports) p7 : p70?p77 (8 ports) p8 : p82?p87 (6 ports) p9 : p93?p97 (5 ports) p10 : p100?p107 (8 ports) p11 : p110?p117 (8 ports) p12 : p124?p127 (4 ports) p13 : p130?p137 (8 ports) p15 : p150, p153 (2 ports) p17 : p174, p175 (2 ports) p22 : p220, p221, p225 (3 ports) port function the input/output ports can individually be set for input or output mode using the direction control register provided for each input/output port. (however, p221 is a can input-only port.) pin function shared with peripheral i/o or external extension signals to serve dual-functions (or shared with two or more peripheral i/o functions to serve triple-functions) pin function p0?p4, p225: depends on the cpu operation mode (that is set by mod0 and mod1 pins). selection p6?p22: as set by each input/output port?s operation mode register. (however, peripheral i/o pin functions are selected by peripheral i/o registers.) note: ? p5, p14, p16, p18-p21 are nonexist. 8.1 outline of input/output ports 8 8-3 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.2 selecting pin functions 8.2 selecting pin functions each input/output port serves dual functions sharing the pin with other internal peripheral i/o or external extension bus signal line (or triple functions sharing the pin with two or more peripheral i/o functions). pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. p0?p4 and p225, when the cpu is set to operate in external extension mode or processor mode, all are switched to serve as signal pins for external access. the cpu operation mode is determined depending on how the mod0 and mod1 pins are set (see the table below). table 8.2.1 cpu operation modes and p0?p4 and p225 pin functions mod0 mod1 operation mode p0?p4 and p225 pin function vss vss single-chip mode input/output port pin vss vcce external extension mode external extension signal pin vcce vss processor mode vcce vcce reserved (use inhibited) ? note: ? vcce and vss are connected to main power supply and gnd, respectively. each input/output port has their functions switched between input/output port pins and internal peripheral i/o pins by setting the respective port operation mode registers. if any internal peripheral i/o has two or more pin functions, use the register provided for that peripheral i/o to select the desired pin function. note that fp and mod1 pin settings during internal flash memory programming do not affect the pin functions. 8 8-4 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.2 selecting pin functions figure 8.2.1 input/output ports and pin function assignments p0 p1 p2 p3 p4 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p5 db0 01 234 567 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 a23 a24 a25 a26 a27 a28 a29 a30 a15 a16 a17 a18 a19 a20 a21 a22 blw#/ ble# bhw#/ bhe# rd# cs0# cs1# a13 a14 (p61) (p62) (p63) bclk/ wr# wait# hreq# hack# rtdtxd/ txd3 (note 2) rtdrxd/ rxd3 (note 2) rtdack/ ctx1 (note 2) rtdclk/ crx1 (note 2) txd0 rxd0 sclki0/ sclko0 txd1 rxd1 sclki1/ sclko1 to16 to17 to18 to19 to20 to11 to12 to13 to14 to15 to10 to9 to8 to3 to4 to5 to6 to7 to2 to1 to0 tclk0 tclk1 tclk2 tclk3 tin16 tin17 tin18 tin19 tin20 tin21 tin22 tin23 p16 p17 txd2 p18 p19 p20 p21 p22 ctx0 crx0 rxd2 tin0 tin3 mod1 (note 3) mod0 (note 3) a12 (note 1) sbi# (note 3) input/output port operation mode setting (reserved) cpu operation mode settings (note 1) note 1: the pin function changes depending on the setting for mod0 and mod1 pins. note 2: these are triple-function pins. their desired output function must be selected using the port peripheral function selec t register. note 3: these ports cannot be used for input/output port function. the sbi#, mod0 and mod1 pin input levels can be read from th ese ports. note: ? p5, p14, p16, p18, p19, p20 and p21 are not provided. 8 8-5 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.3 input/output port related registers the input/output port related registers included in the microcomputer consists of the port data register, port direc- tion register and port operation mode register. note that p5 is reserved for future use. the tables below show an input/output port related register map. input/output port related register map (1/2) address +0 address +1 address see pages b0 b7 b8 b15 h'0080 0700 p0 data register p1 data register 8-7 (p0data) (p1data) h'0080 0702 p2 data register p3 data register 8-7 (p2data) (p3data) h'0080 0704 p4 data register (use inhibited area) 8-7 (p4data) h'0080 0706 p6 data register p7 data register 8-7 (p6data) (p7data) h'0080 0708 p8 data register p9 data register 8-7 (p8data) (p9data) h'0080 070a p10 data register p11 data register 8-7 (p10data) (p11data) h'0080 070c p12 data register p13 data register 8-7 (p12data) (p13data) h'0080 070e (use inhibited area) p15 data register 8-7 (p15data) h'0080 0710 (use inhibited area) p17 data register 8-7 (p17data) h'0080 0712 (use inhibited area) (use inhibited area) h'0080 0714 (use inhibited area) (use inhibited area) h'0080 0716 p22 data register (use inhibited area) 8-7 (p22data) (use inhibited area) h'0080 0720 p0 direction register p1 direction register 8-8 (p0dir) (p1dir) h'0080 0722 p2 direction register p3 direction register 8-8 (p2dir) (p3dir) h'0080 0724 p4 direction register (use inhibited area) 8-8 (p4dir) h'0080 0726 p6 direction register p7 direction register 8-8 (p6dir) (p7dir) h'0080 0728 p8 direction register p9 direction register 8-8 (p8dir) (p9dir) h'0080 072a p10 direction register p11 direction register 8-8 (p10dir) (p11dir) h'0080 072c p12 direction register p13 direction register 8-8 (p12dir) (p13dir) h'0080 072e (use inhibited area) p15 direction register 8-8 (p15dir) h'0080 0730 (use inhibited area) p17 direction register 8-8 (p17dir) h'0080 0732 (use inhibited area) (use inhibited area) h'0080 0734 (use inhibited area) (use inhibited area) h'0080 0736 p22 direction register (use inhibited area) 8-8 (p22dir) 8.3 input/output port related registers | 8 8-6 input/output ports and pin functions 32176 group user?s manual (rev.1.01) input/output port related register map (2/2) address +0 address +1 address see pages b0 b7 b8 b15 h'0080 0744 (use inhibited area) port input special function control register 8-15 (picnt) h'0080 0746 (use inhibited area) p7 operation mode register 8-9 (p7mod) h'0080 0748 p8 operation mode register p9 operation mode register 8-9 (p8mod) (p9mod) 8-10 h'0080 074a p10 operation mode register p11 operation mode register 8-10 (p10mod) (p11mod) 8-11 h'0080 074c p12 operation mode register p13 operation mode register 8-11 (p12mod) (p13mod) 8-12 h'0080 074e (use inhibited area) p15 operation mode register 8-12 (p15mod) h'0080 0750 (use inhibited area) p17 operation mode register 8-13 (p17mod) h'0080 0752 (use inhibited area) (use inhibited area) h'0080 0754 (use inhibited area) (use inhibited area) h'0080 0756 p22 operation mode register (use inhibited area) 8-13 (p22mod) (use inhibited area) h'0080 0760 port group 0,1 input level setting register port group 3 input level setting register 8-18 (pg01lev) (pg3lev) h'0080 0762 port group 4,5 input level setting register port group 6,7 input level setting register 8-18 (pg45lev) (pg67lev) h'0080 0764 port group 8 input level setting register (use inhibited area) 8-18 (pg8lev) h'0080 0766 (use inhibited area) p7 peripheral function select register 8-14 (p7smod) 8.3 input/output port related registers | 8 8-7 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.3.1 port data registers p0 data register (p0data) 8 8-8 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.3.2 port direction registers p0 direction register (p0dir) 8 8-9 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.3.3 port operation mode registers p7 operation mode register (p7mod) 8 8-10 input/output ports and pin functions 32176 group user?s manual (rev.1.01) p9 operation mode register (p9mod) 8 8-11 input/output ports and pin functions 32176 group user?s manual (rev.1.01) p11 operation mode register (p11mod) 8 8-12 input/output ports and pin functions 32176 group user?s manual (rev.1.01) p13 operation mode register (p13mod) < address: h?0080 074d> 8 8-13 input/output ports and pin functions 32176 group user?s manual (rev.1.01) p17 operation mode register (p17mod) 8 8-14 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.3 input/output port related registers 8.3.4 port peripheral function select register p7 peripheral function select register (p7smod) 8 8-15 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.3.5 port input special function control register port input special function control register (picnt) 8 8-16 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.3 input/output port related registers read xstat (1) to know whether xin oscillation has ever stopped after being reset write xstat = 0 (2) to know the current status of xin oscillation wait for 20 cpu clock periods or more read xstat wait before inspecting xstat figure 8.3.1 procedure for setting xstat (2) pisel (port input data select) bit (bit 14) when the port direction register is set for output, this bit selects the target data to be read from the port data register. at this time, this bit is unaffected by the port operation mode register. table 8.3.1 pisel bit settings and the target data to be read from the port data register direction register pisel settings target data to be read 0 (input) 0/1 port pin level 1 (output) 0 port output latch 1 port pin level 8 8-17 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.3 input/output port related registers (3) pien0 (port input enable) bit (bit 15) this bit is used to prevent current from flowing into the port input pins. because the input/output ports are disabled against input after reset, if any ports need to be used in input mode they must be enabled for input by setting this bit to "1". when disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. consequently, if a peripheral input function is selected for any port while disabled against input by using the port operation mode register, the port may operate unexpectedly due to the low- level input on it. the following shows the procedure for selecting a peripheral input function. (1) enable the port for input when its pin level is valid (high or low) (2) select a function using the port operation mode bit during boot mode, the pins shared with serial i/o functions are enabled for input and can therefore be protected against current flowing in from the pins other than serial i/o functions during flash programming by clearing pien0. the table below lists the pins that can be controlled by the pien0 bit in each operation mode. table 8.3.2 pins controllable by pien0 bit mode name controllable pins uncontrolled pins p00?p07, p10?p17, p20?p27 p221, fp, sbi#, mod0, mod1, mod2, reset# p30?p37, p41?p47, p61?p63 single-chip p70?p77, p82?p87, p93?p97 p100?p107, p110?p117, p124?p127 p130?p137, 150, p153, p174, p175 p220, p225 p61?p63, p70?p77, p82?p87 p00?p07, p10?p17 external extension p93?p97, p100?p107, p110?p117 p20?p27, p30?p37 microprocessor p124?p127, p130?p137 p41?p47, p221, p225 p150, p153, p174, p175, p220 fp, sbi#, mod0, mod1, mod2, reset# p00?p07, p10?p17, p20?p27 p82?p87, p174, p175 boot p30?p37, p41?p47, p61?p63 p221, fp, sbi#, mod0, mod1, mod2, reset# (single-chip) p67, p70?p77, p93?p97 p100?p107, p110?p117, p124?p127 p130?p137, p150, p153, p220, p225 8 8-18 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.4 port input level switching function the port input level switching function allows the port threshold to be switched to one of three voltage levels (with or without schmitt as selected) in units of the following port group. this can be set to the following registers in units of group . group 0: p00?p07, p10?p17, p20?p27, p30?p37, p41?p47, p70?p73, p225 group 1: p82?p87, p174?p177 group 3: p93?p97, p110?p117 group 4: p124?p127 group 5: p61?p63, sbi# group 6: p74?p77, p100?p107 group 7: p220, p221 group 8: p130?p137, p150?p153 port group 0,1 input level setting register (pg01lev) 8 8-19 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.4 port input level switching function 8 8-20 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.5 port peripheral circuits figures 8.5.1 through 8.5.5 show the peripheral circuit diagrams of the input/output ports described in the preceding pages. figure 8.5.1 port peripheral circuit diagram (1) p00?p07(db0?db7) p10?p17(db8?db15) p20?p27(a23?a30) p30?p37(a15?a22) p41(blw#/ble#) p42(bhw#/bhe#) p43(rd#) p44(cs0#) p45(cs1#) p46?p47(a13?a14) p61?p63 p225(a12) p83(rxd0) p86(rxd1) p124?p127(tclk0?tclk3) p150, p153(tin0, tin3) p175(rxd2) note 1: for details about the port level switching function, see section 8.4, "port input level switching function." notes: during external extension and processor modes, p00-p07, p10-p17, p20-p27, p30-p37, p41-p47, and p225 are external bus interface control signal pins, but their functional description in this block diagram is omitted. the circle denotes a pin. the symbol denotes a parasitic diode. make sure the voltage applied to each pin does not exceed the vcce voltage. the input capacitance of each pin is approximately 10 pf. data bus data bus port output latch input function enable peripheral function input direction register direction register port output latch operation mode register port level switching function (standard: peripheral ttl) (note 1) (note 1) input function enable port level switching function (standard: peripheral schmitt) 8.5 port peripheral circuits 8 8-21 input/output ports and pin functions 32176 group user?s manual (rev.1.01) figure 8.5.2 port peripheral circuit diagram (2) 8.5 port peripheral circuits sbi# p221/crx data bus sbi# , crx p72(hreq#) hreq# data bus direction register port output latch operation mode register port level switching function (standard: peripheral schmitt) (note 1) port level switching function (standard: peripheral schmitt) (note 1) p71(wait#) data bus wait# direction register port output latch operation mode register port level switching function (standard: peripheral schmitt) input function enable (note 1) input function enable note 1: for details about the port level switching function, see section 8.4, "port input level switching function." notes: the circle denotes a pin. the symbol denotes a parasitic diode. make sure the voltage applied to each pin does not exceed the vcce voltage. the input capacitance of each pin is approximately 10 pf. 8 8-22 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.5 port peripheral circuits p70(bclk/wr#) p73(hack#) p76(rtdack) p82(txd0) p85(txd1) p93?p97(to16?to20) p100?p107(to8?to15) p110?p117(to0?to7) p174(txd2) p220(ctx0) data bus peripheral function output direction register port output latch operation mode register port level switching function (standard: peripheral schmitt) input function enable (note 1) p84(sclki0,sclko0) p87(sclki1,sclko1) data bus sclkii input sclkoi output direction register port output latch operation mode register port level switching function (standard: peripheral schmitt) input function enable (note 1) uart/csio function select bit internal/external clock select bit note 1: for details about the port level switching function, see section 8.4, "port input level switching function." notes: the circle denotes a pin. the symbol denotes a parasitic diode. make sure the voltage applied to each pin does not exceed the vcce voltage. the input capacitance of each pin is approximately 10 pf. figure 8.5.3 port peripheral circuit diagram (3) 8 8-23 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.5 port peripheral circuits figure 8.5.4 port peripheral circuit diagram (4) reset# xin jtrst reset#, xin, jtrst mod0 mod1 mod0, mod1 fp fp jtdi jtck jtms jtdi, jtck, jtms jtdo jtdo vcci vcce vdd avcc0 vcci, vcce, vdd , avcc0 ad0in0?15 vref0 xout ad0in0?15, vref0, xout notes: the circle denotes a pin. the symbol denotes a parasitic diode. make sure the voltage applied to each pin does not exceed the vcce voltage. the input capacitance of each pin is approximately 10 pf. 8 8-24 input/output ports and pin functions 32176 group user?s manual (rev.1.01) figure 8.5.5 port peripheral circuit diagram (5) p75(rtdrxd/rxd3) p77(rtdclk/crx1) p74(rtdtxd/txd3) p76(rtdack/cxt1) data bus peripheral function input 2 peripheral function input 1 direction register port output latch operation mode register port level switching function (standard: peripheral schmitt) input function enable (note 1) p7 peripheral function select register data bus peripheral function output 2 peripheral function output 1 direction register port output latch operation mode register port level switching function (standard: no peripheral input) input function enable (note 1) p7 peripheral function select register note 1: for details about the port level switching function, see section 8.4, "port input level switching function." notes: the circle denotes a pin. the symbol denotes a parasitic diode. make sure the voltage applied to each pin does not exceed the vcce voltage. the input capacitance of each pin is approximately 10 pf. 8.5 port peripheral circuits 8 8-25 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.6 precautions on input/output ports ? when using input/output ports in output mode because the value of the port data register is undefined when exiting the reset state, the port data register must have its initial value set in it before the port direction register can be set for output. conversely, if the port direction register is set for output before setting data in the port data register, the port data register outputs an undefined value until any data is written into it. ? about the port input disable function because the input/output ports are disabled against input after reset, they must be enabled for input by setting the port input enable (pien0) bit to "1" before their input functions can be used. when disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. consequently, if a peripheral input function is selected for any port while disabled against input by using the port operation mode register, the port may operate unexpectedly due to the low-level input on it. 8.6 precautions on input/output ports 8 8-26 input/output ports and pin functions 32176 group user?s manual (rev.1.01) 8.6 precautions on input/output ports this page is blank for reasons of layout. chapter 9 dmac 9.1 outline of the dmac 9.2 dmac related registers 9.3 functional description of the dmac 9.4 precautions about the dmac 9 9-2 dmac 32176 group user?s manual (rev.1.01) 9.1 outline of the dmac the microcomputer internally contains a 10-channel dmac (direct memory access controller). it allows data to be transferred at high speed between internal peripheral i/os, between internal ram and internal peripheral i/o, or between internal rams, as initiated by a software trigger or requested from an internal peripheral i/o. table 9.1.1 outline of the dmac item description number of channels 10 channels transfer request sources ? software trigger ? request from internal peripheral i/os: a-d converter, multijunction timer, serial i/o (reception completed, transmit buffer empty) or can ? dma channels can be cascaded (note 1) maximum number of 256 times times transferred transferable address ? 64 kbytes (address space from h?0080 0000 to h?0080 ffff) space ? transfers between in ternal peripheral i/os, between internal ram and internal peripheral i/o, and between internal rams are supported. transfer data size 16 or 8 bits transfer method single transfer dma (control of the internal bus is relinquished for each transfer performed), dual- address transfer transfer mode single transfer mode direction of transfer one of three modes can be selected for the source and destination: ? address fixed ? address incremental ? ring buffered channel priority dma0 > dma1 > dma2 > dma3 > dma4 > dma5 > dma6 > dma7 > dma8 > dma9 (priority is fixed) maximum transfer rate 13.3 mbytes per second (when internal peripheral clock bclk = 20 mhz) interrupt request group interrupt request can be generated when each transfer count register underflows. transfer area 64 kbytes from h?0080 0000 to h?0080 ffff note 1: the dma channels can be cascaded in the manner described below. ? start dma transfer on dma1 upon completion of one dma transfer on dma0 ? start dma transfer on dma2 upon completion of one dma transfer on dma1 ? start dma transfer on dma0 upon completion of one dma transfer on dma2 ? start dma transfer on dma4 upon completion of one dma transfer on dma3 ? start dma transfer on dma6 upon completion of one dma transfer on dma5 ? start dma transfer on dma7 upon completion of one dma transfer on dma6 ? start dma transfer on dma5 upon completion of one dma transfer on dma7 ? start dma transfer on dma9 upon completion of one dma transfer on dma8 ? start dma transfer on dma5 upon completion of all dma transfers on dma0 (upon underflow of the transfer count register) 9.1 outline of the dmac 9 dmac 9-3 32176 group user?s manual (rev.1.01) figure 9.1.1 block diagram of the dmac 9.1 outline of the dmac s dma0 udf end dma1 udf end dma2 udf end dma3 udf end dma4 udf end dma5 udf end dma6 udf end dma7 udf end dma8 udf end dma9 udf end s s s s s s s s s ad0 conversion completed tio8_udf software start software start software start sio0_txd sio1_rxd software start sio0_rxd software start software start dma0?4 interrupt dma5?9 interrupt sio2_rxd sio1_txd software start sio2_txd software start sio3_rxd software start can0_s0/s15 (note 1) tin0(p150) (note 1) tin19(p133) (note 1) tin20(p134) sio3_txd software start (note 1) tin18(p132) can0_s1/s14 can1_s0/s15 can1_s1/s14 note 1: indicates edge select output at the timer input pin. 0123 input event bus output event bus 3210 3210 0123 9 9-4 dmac 32176 group user?s manual (rev.1.01) 9.2 dmac related registers the diagram below shows a memory map of the dmac related registers. dmac related register map (1/2) address +0 address +1 address see pages b0 b7 b8 b15 h'0080 0400 dma0?4 interrupt request status register dma0?4 interrupt request mask register 9-18 (dm04itst) (dm04itmk) 9-19 (use inhibited area) h'0080 0408 dma5?9 interrupt request status register dma5?9 interrupt request mask register 9-18 (dm59itst) (dm59itmk) 9-19 (use inhibited area) h'0080 0410 dma0 channel control register dma0 transfer count register 9-6 (dm0cnt) (dm0tct) 9-15 h'0080 0412 dma0 source address register 9-13 (dm0sa) h'0080 0414 dma0 destination address register 9-14 (dm0da) h'0080 0416 (use inhibited area) h'0080 0418 dma5 channel control register dma5 transfer count register 9-8 (dm5cnt) (dm5tct) 9-15 h'0080 041a dma5 source address register 9-13 (dm5sa) h'0080 041c dma5 destination address register 9-14 (dm5da) h'0080 041e (use inhibited area) h'0080 0420 dma1 channel control register dma1 transfer count register 9-6 (dm1cnt) (dm1tct) 9-15 h'0080 0422 dma1 source address register 9-13 (dm1sa) h'0080 0424 dma1 destination address register 9-14 (dm1da) h'0080 0426 (use inhibited area) h'0080 0428 dma6 channel control register dma6 transfer count register 9-9 (dm6cnt) (dm6tct) 9-15 h'0080 042a dma6 source address register 9-13 (dm6sa) h'0080 042c dma6 destination address register 9-14 (dm6da) h'0080 042e (use inhibited area) h'0080 0430 dma2 channel control register dma2 transfer count register 9-7 (dm2cnt) (dm2tct) 9-15 h'0080 0432 dma2 source address register 9-13 (dm2sa) h'0080 0434 dma2 destination address register 9-14 (dm2da) h'0080 0436 (use inhibited area) h'0080 0438 dma7 channel control register dma7 transfer count register 9-9 (dm7cnt) (dm7tct) 9-15 h'0080 043a dma7 source address register 9-13 (dm7sa) h'0080 043c dma7 destination address register 9-14 (dm7da) h'0080 043e (use inhibited area) 9.2 dmac related registers | | 9 dmac 9-5 32176 group user?s manual (rev.1.01) 9.2 dmac related registers dmac related register map (2/2) address +0 address +1 address see pages b0 b7 b8 b15 h'0080 0440 dma3 channel control register dma3 transfer count register 9-7 (dm3cnt) (dm3tct) 9-15 h'0080 0442 dma3 source address register 9-13 (dm3sa) h'0080 0444 dma3 destination address register 9-14 (dm3da) h'0080 0446 (use inhibited area) h'0080 0448 dma8 channel control register dma8 transfer count register 9-10 (dm8cnt) (dm8tct) 9-15 h'0080 044a dma8 source address register 9-13 (dm8sa) h'0080 044c dma8 destination address register 9-14 (dm8da) h'0080 044e (use inhibited area) h'0080 0450 dma4 channel control register dma4 transfer count register 9-8 (dm4cnt) (dm4tct) 9-15 h'0080 0452 dma4 source address register 9-13 (dm4sa) h'0080 0454 dma4 destination address register 9-14 (dm4da) h'0080 0456 (use inhibited area) h'0080 0458 dma9 channel control register dma9 transfer count register 9-10 (dm9cnt) (dm9tct) 9-15 h'0080 045a dma9 source address register 9-13 (dm9sa) h'0080 045c dma9 destination address register 9-14 (dm9da) h'0080 045e (use inhibited area) h'0080 0460 dma0 software request generation register 9-12 (dm0sri) h'0080 0462 dma1 software request generation register 9-12 (dm1sri) h'0080 0464 dma2 software request generation register 9-12 (dm2sri) h'0080 0466 dma3 software request generation register 9-12 (dm3sri) h'0080 0468 dma4 software request generation register 9-12 (dm4sri) (use inhibited area) h'0080 0470 dma5 software request generation register 9-12 (dm5sri) h'0080 0472 dma6 software request generation register 9-12 (dm6sri) h'0080 0474 dma7 software request generation register 9-12 (dm7sri) h'0080 0476 dma8 software request generation register 9-12 (dm8sri) h'0080 0478 dma9 software request generation register 9-12 (dm9sri) | 9 9-6 dmac 32176 group user?s manual (rev.1.01) 9.2.1 dma channel control registers dma0 channel control register (dm0cnt) 9 dmac 9-7 32176 group user?s manual (rev.1.01) dma2 channel control register (dm2cnt) 9 9-8 dmac 32176 group user?s manual (rev.1.01) dma4 channel control register (dm4cnt) 9 dmac 9-9 32176 group user?s manual (rev.1.01) dma6 channel control register (dm6cnt) 9 9-10 dmac 32176 group user?s manual (rev.1.01) dma8 channel control register (dm8cnt) 9 dmac 9-11 32176 group user?s manual (rev.1.01) 9.2 dmac related registers the dma channel control register consists of the bits to select dma transfer mode on each channel, set the dma transfer request flag, select the cause or source of dma request and enable dma transfer, as well as those to set the transfer size and the source/destination address directions. (1) mdseln (dman transfer mode select) bit (bit 0) when performing dma transfer in single transfer mode, this bit selects normal mode or ring buffer mode. setting this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode. in ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is returned back to the transfer start address, from which transfer operation is repeated. in this case, the transfer count register counts in free-run mode, during which time transfer operation is continued until the transfer enable bit is reset to "0" (to disable transfer). in ring buffer mode, no interrupt is generated at completion of dma transfer. (2) treqfn (dman transfer request flag) bit (bit 1) this flag is set to "1" when a dma transfer request occurs, and is cleared to "0" when the transfer for that transfer request is completed. reading this flag helps to know dma transfer requests on each channel. writing "0" to this bit clears the generated dma transfer request. writing "1" has no effect; the bit retains the value it had before the write. if a new dma transfer request occurs on a channel for which the dma transfer request flag has already been set to "1", the next dma transfer request is not accepted until the transfer being performed on that channel is completed. (3) reqsln (dman request source select) bits (bits 2?3) these bits select the cause or source of dma request on each dma channel. (4) tenln (dman transfer enable) bit (bit 4) setting this bit to "1" enables transfer, and the channel is made ready for dma transfer. when all transfers on that channel are completed (i.e., the transfer counter register underflows), the bit is cleared to "0". setting this bit to "0" disables transfer. however, if a transfer request has already been accepted, transfers on that channel are not disabled until after the requested transfer is completed. (5) tszsln (dman transfer size select) bit (bit 5) this bit selects the number of bits to be transferred in one dma transfer operation (the unit of one transfer). the unit of one transfer is 16 bits when tszsl = "0" or 8 bits when tszsl = "1". (6) sadsln (dman source address direction select) bit (bit 6) this bit selects the direction in which the source address changes. this mode can be selected from two choices: address fixed or address incremental. (7) dadsln (dman destination address direction select) bit (bit 7) this bit selects the direction in which the destination address changes. this mode can be selected from two choices: address fixed or address incremental. 9 9-12 dmac 32176 group user?s manual (rev.1.01) 9.2 dmac related registers 9.2.2 dma software request generation registers dma0 software request generation register (dm0sri) 9 dmac 9-13 32176 group user?s manual (rev.1.01) 9.2.3 dma source address registers dma0 source address register (dm0sa) 9 9-14 dmac 32176 group user?s manual (rev.1.01) 9.2.4 dma destination address registers dma0 destination address register (dm0da) 9 dmac 9-15 32176 group user?s manual (rev.1.01) 9.2.5 dma transfer count registers dma0 transfer count register (dm0tct) 9 9-16 dmac 32176 group user?s manual (rev.1.01) 9.2 dmac related registers 9.2.6 dma interrupt related registers the dma interrupt related registers are used to control the interrupt request signals sent from the dmac to the interrupt controller. (1) interrupt request status bit this status bit is used to determine whether there is an interrupt request. when an interrupt request occurs, this bit is set in hardware (cannot be set in software). the status bit is cleared by writing "0". writing "1" has no effect; the bit retains the status it had before the write. because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. in interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. if the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) interrupt request mask bit this bit is used to disable unnecessary interrupt requests within the grouped interrupt request. set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests. figure 9.2.1 interrupt request status and mask registers to the interrupt controller interrupt request from each peripheral function interrupt request status data bus set group interrupt interrupt request enabled clear f/f f/f data = 0 9 dmac 9-17 32176 group user?s manual (rev.1.01) 9.2 dmac related registers figure 9.2.2 example for clearing interrupt request status b4 5 b7 interrupt request status initial state event occurs on bit 6 interrupt request event occurs on bit 4 only bit 6 cleared bit 4 data retained b4 5 b7 1 1 0 1 write to the interrupt request status example for clearing interrupt request status 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 program example istreg = 0xfd; /* clear istat1 (0x02 bit) only */ to clear the interrupt request status register 0 (istreg) interrupt request status 1, istat1 (0x02 bit) to clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. at this time, avoid using a logic operation like the one shown below. because it requires three step-istreg read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared. b4 5 6 b7 interrupt request status event occurs on bit 6 event occurs on bit 4 only bit 6 cleared bit 4 also cleared 0 0 1 0 1 0 1 0 0 0 0 0 read 0 0 1 0 0 0 0 0 clear bit 6 (and'ing with 1101) write 6 6 istreg &= 0xfd; /* clear istat1 (0x02 bit) only */ 9 9-18 dmac 32176 group user?s manual (rev.1.01) 9.2 dmac related registers dma0?4 interrupt request status register (dm04itst) 9 dmac 9-19 32176 group user?s manual (rev.1.01) 9.2 dmac related registers dma0?4 interrupt request mask register (dm04itmk) 9 9-20 dmac 32176 group user?s manual (rev.1.01) f/f f/f dmitmk0 dmitst0 f/f f/f dmitmk1 dmitst1 f/f f/f dmitmk2 dmitst2 f/f f/f dmitmk3 dmitst3 f/f f/f dmitmk4 dmitst4 b15 b7 b14 b6 b13 b5 b12 b4 b11 b3 data bus dma4udf dma3udf dma2udf dma1udf dma0udf dma transfer interrupt request 0 (level) 5-source inputs dm04itst (h'0080 0400) dm04itmk (h'0080 0401) figure 9.2.3 block diagram of dma transfer interrupt request 0 9.2 dmac related registers 9 dmac 9-21 32176 group user?s manual (rev.1.01) f/f f/f dmitmk5 dmitst5 f/f f/f dmitmk6 dmitst6 f/f f/f dmitmk7 dmitst7 f/f f/f dmitmk8 dmitst8 f/f f/f dmitmk9 dmitst9 b15 b7 b14 b6 b13 b5 b12 b4 b11 b3 data bus dma9udf dma8udf dma7udf dma6udf dma5udf dma transfer interrupt request 1 (level) 5-source inputs dm59itst (h'0080 0408) dm59itmk (h'0080 0409) figure 9.2.4 block diagram of dma transfer interrupt request 1 9.2 dmac related registers 9 9-22 dmac 32176 group user?s manual (rev.1.01) 9.3 functional description of the dmac 9.3.1 dma transfer request sources for each dma channel (channels 0?9), dma transfer can be requested from two or more sources. there are various causes or sources of dma transfer request, so that dma transfer can be started by a request from some internal peripheral i/o, started in software by a program, or can be started upon completion of one transfer or all transfers on another dma channel (cascade mode). the causes or sources of dma transfer requests are selected using the request source select bits reqsln on each channel (dman channel control register bits 2 and 3). the tables below list the causes or sources of dma transfer requests on each channel. table 9.3.1 dma transfer request sources and generation timings on dma0 reqsl0 dma transfer request source dma transfer request generation timing 0 0 software start or one dma2 when any data is written to the dma0 software request generation register transfer completed (software start) or when one dma2 transfer is completed (cascade mode) 0 1 a-d0 conversion completed when a-d0 conversion is completed 1 0 mjt (tio8_udf) when mjt tio8 underflows 1 1 mjt (input event bus 2) when mjt input event bus 2 signal is generated table 9.3.2 dma transfer request sources and generation timings on dma1 reqsl1 dma transfer request source dma transfer request generation timing 0 0 software start when any data is written to the dma1 software request generation register 0 1 mjt (output event bus 0) when mjt output event bus 0 signal is generated 1 0 settings inhibited ? 1 1 one dma0 transfer completed when one dma0 transfer is completed (cascade mode) table 9.3.3 dma transfer request sources and generation timings on dma2 reqsl2 dma transfer request source dma transfer request generation timing 0 0 software start when any data is written to the dma2 software request generation register 0 1 mjt (output event bus 1) when mjt output event bus 1 signal is generated 1 0 mjt (tin18 edge select output) when mjt tin18 input signal is generated (edge select output) 1 1 one dma1 transfer completed when one dma1 transfer is completed (cascade mode) 9.3 functional description of the dmac 9 dmac 9-23 32176 group user?s manual (rev.1.01) table 9.3.4 dma transfer request sources and generation timings on dma3 reqsl3 dma transfer request source dma transfer request generation timing 0 0 software start when any data is written to the dma3 software request generation register 0 1 serial i/o0 (transmit buffer empty) when serial i/o0 transmit buffer is empty 1 0 serial i/o1 (reception completed) when serial i/o1 reception is completed 1 1 mjt (tin0 edge select output) when mjt tin0 input signal is generated (edge select output) table 9.3.5 dma transfer request sources and generation timings on dma4 reqsl4 dma transfer request source dma transfer request generation timing 0 0 software start when any data is written to the dma4 software request generation register 0 1 one dma3 transfer completed when one dma3 transfer is completed (cascade mode) 1 0 serial i/o0 (reception completed) when serial i/o0 reception is completed 1 1 mjt (tin19 edge select output) when mjt tin19 input signal is generated (edge select output) table 9.3.6 dma transfer request sources and generation timings on dma5 reqsl5 dma transfer request source dma transfer request generation timing 0 0 software start or one dma7 when any data is written to the dma5 software request generation register transfer completed (software start) or when one dma7 transfer is completed (cascade mode) 0 1 all dma0 transfers completed when all dma0 transfers are completed (cascade mode) 1 0 serial i/o2 (reception completed) when serial i/o2 reception is completed 1 1 mjt (tin20 edge select output) when mjt tin20 input signal is generated (edge select output) table 9.3.7 dma transfer request sources and generation timings on dma6 reqsl6 dma transfer request source dma transfer request generation timing 0 0 software start when any data is written to the dma6 software request generation register 0 1 serial i/o1 (transmit buffer empty) when serial i/o1 transmit buffer is empty 1 0 can (can0_s0/s15) can0: when slot 0 transmission failed or slot 15 transmission/reception completed 1 1 one dma5 transfer completed when one dma5 transfer is completed (cascade mode) 9.3 functional description of the dmac 9 9-24 dmac 32176 group user?s manual (rev.1.01) 9.3 functional description of the dmac table 9.3.8 dma transfer request sources and generation timings on dma7 reqsl7 dma transfer request source dma transfer request generation timing 0 0 software start when any data is written to the dma7 software request generation register 0 1 serial i/o2 (transmit buffer empty) when serial i/o2 transmit buffer is empty 1 0 can (can0_s1/s14) can0: when slot 1 transmission failed or slot 14 transmission/reception completed 1 1 one dma6 transfer completed when one dma6 transfer is completed (cascade mode) table 9.3.9 dma transfer request sources and generation timings on dma8 reqsl8 dma transfer request source dma transfer request generation timing 0 0 software start when any data is written to the dma8 software request generation register 0 1 mjt (input event bus 0) when mjt input event bus 0 signal is generated 1 0 serial i/o3 (reception completed) when serial i/o3 reception is completed 1 1 can (can1_s0/s15) can1: when slot 0 transmission failed or slot 15 transmission/reception completed table 9.3.10 dma transfer request sources and generation timings on dma9 reqsl9 dma transfer request source dma transfer request generation timing 0 0 software start when any data is written to the dma9 software request generation register 0 1 serial i/o3 (transmit buffer empty) when serial i/o3 transmit buffer is empty 1 0 can (can1_s1/s14) can1: when slot 1 transmission failed or slot 14 transmission/reception completed 1 1 one dma8 transfer completed when one dma8 transfer is completed (cascade mode) 9 dmac 9-25 32176 group user?s manual (rev.1.01) dma transfer starts as requested by internal peripheral i/o dma transfer processing starts transfer count register underflows interrupt request generated set dma0 channel control register set dma0-4 interrupt request status register set dma0 channel control register set dma0 source address register set dma0 destination address register set dma0 count register setting dmac-related registers starting dma transfer dma transfer completed transfers disabled interrupt request status bits cleared set dma0-4 interrupt request mask register source address of transfer destination address of transfer number of times dma transfer is performed transfer mode, request source, transfer size, address direction and transfer enable dma operation completed interrupt request enabled set the interrupt controller's dma0-4 interrupt control register interrupt priority level setting interrupt controller-related registers figure 9.3.1 example of a dma transfer processing procedure 9.3.2 dma transfer processing procedure shown below is an example of how to control dma transfer in cases when performing transfer on dma channel 0. 9.3 functional description of the dmac 9 9-26 dmac 32176 group user?s manual (rev.1.01) figure 9.3.2 gaining and releasing control of the internal bus one dma transfer dmac cpu internal bus arbitration (requests from the dmac) internal bus r: read w: write rw rw rw requested gained requested gained requested gained one dma transfer one dma transfer released released released 9.3 functional description of the dmac 9.3.3 starting dma use the reqsl (dma request source select) bit to set the cause or source of dma transfer request. to enable dma, set the tenl (dma transfer enable) bit to "1". dma transfer begins when the specified cause or source of dma transfer request becomes effective after setting the tenl (dma transfer enable) bit to "1". note: ? if the transfer request source selected by the reqsl (dma transfer request source select) bit is mjt (tin input signal), the time required for dma transfer to begin after detecting the rising or falling or both edges of the tin input signal is three cycles (150 ns when the internal peripheral clock = 20 mhz) at the shortest. or, depending on the preceding or following bus usage condition, up to six cycles (300 ns when the internal peripheral clock = 20 mhz) may be required. (however, this applies when the external bus, hold and the lock instruction all are unused.) to ensure that changes of the tin input signal state will be detected correctly, make sure the tin input signal is held active for a duration of more than 7tc (bclk)/2. (for details, see section 21.8, ?ac characteristics (when vcce = 5 v),? and section 21.9, ?ac characteristics (when vcce = 3.3 v).?) 9.3.4 dma channel priority channel 0 has the highest priority. the priority of this and other channels is shown below. channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel 6 > channel 7 > channel 8 > channel 9 this order of priority is fixed. channel priority is resolved every transfer cycle (i.e., every three dma buy cycles), and the channel with the highest priority among those that are requesting a dma transfer is selected. 9.3.5 gaining and releasing control of the internal bus for any channel, control of the internal bus is gained and released in ?single transfer dma? mode. in single transfer dma, the dmac gains control of the internal bus (in one peripheral clock cycle) when dma transfer request is accepted and after executing one dma transfer (in one read and one write peripheral clock cycle), returns bus control to the cpu. the diagram below shows the operation in single transfer dma. 9 dmac 9-27 32176 group user?s manual (rev.1.01) 9.3.6 transfer units use the tszsl (dma transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one dma transfer. 9.3.7 transfer counts use the dma transfer count register to set transfer counts for each channel. transfer can be performed up to 256 times. the value of the dma transfer count register is decremented by one every time one transfer unit is transferred. in ring buffer mode, the dma transfer count register operates in free-run mode, with the value set in it ignored. 9.3.8 address space the address space in which data can be transferred by dma is 64 kbytes of internal peripheral i/o or ram space (h?0080 0000 through h?0080 ffff) for both source and destination. to set the source and destination addresses on each dma channel, use the dma source address register and dma destination address register. 9.3.9 transfer operation (1) dual-address transfer irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (the transfer data is taken into the dmac?s internal temporary register before being transferred.) (2) bus protocol and bus timing because the bus interface is shared with the cpu, dma transfer is performed with the same bus protocol and the same bus timing as when peripheral modules are accessed by the cpu. (3) transfer rate transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the bus and one read and one write cycle to perform one transfer. therefore, the maximum transfer rate is calculated by the equation below: maximum transfer rate [bytes per second] = 2 bytes 9.3 functional description of the dmac 9 9-28 dmac 32176 group user?s manual (rev.1.01) figure 9.3.3 transfer byte positions 9.3 functional description of the dmac (4) address count direction and address changes the direction in which the source and destination addresses are counted as transfer proceeds (?address fixed? or ?address incremental?) is set for each channel using the sadsl (source address direction select) and dadsl (destination address direction select) bits. when the transfer size is 16 bits, the address is incremented by two for each dma transfer performed; when the transfer size is 8 bits, the address is incremented by one. table 9.3.11 address count direction and address changes address count direction transfer unit address change for one dma address fixed 8 bits 0 16 bits 0 address incremental 8 bits +1 16 bits +2 (5) transfer count value the transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits). (6) transfer byte positions when the transfer unit is 8 bits, the lsb of the address register is effective for both source and destination. (therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address or vice versa.) when the transfer unit is 16 bits, the lsb of the address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. the diagram below shows the valid byte positions in dma transfer. b0 b7 b8 b15 8 bits +0 +1 source destination 9 dmac 9-29 32176 group user?s manual (rev.1.01) 9.3 functional description of the dmac figure 9.3.4 example of how addresses are incremented in 32-channel ring buffer mode 9 9-30 dmac 32176 group user?s manual (rev.1.01) 9.3.10 end of dma and interrupt in normal mode, dma transfer is terminated by an underflow of the transfer count register. when transfer finishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. also, an interrupt request is generated at completion of transfer. however, if interrupt requests on any channel have been masked by the dma interrupt request mask register, no interrupt requests are generated on that channel. during ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). in this case, therefore, no interrupt requests are gener- ated at completion of dma transfer. nor are these dma transfer-completed interrupt requests are generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit. 9.3.11 each register status after completion of dma transfer when dma transfer is completed, the status of the source and destination address registers becomes as fol- lows: (1) address fixed ? the values set in the address registers before dma transfer started remain intact (fixed). (2) address incremental ? for 8-bit transfer, the values of the address registers are the last transfer address + 1. ? for 16-bit transfer, the values of the address registers are the last transfer address + 2. the transfer count register at completion of dma transfer is in an underflow state (h?ff). therefore, before another dma transfer can be performed, the transfer count register must be set newly again, except when trying to perform transfers 256 times (h?ff). 9.3 functional description of the dmac 9 dmac 9-31 32176 group user?s manual (rev.1.01) 9.4 precautions about the dmac ? about writing to the dmac related registers because dma transfer involves exchanging data via the internal bus, the dmac related registers basically can only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0"). when transfer is enabled, do not write to the dmac related registers, except the dma transfer enable bit, the transfer request flag and the dma transfer count register that is protected in hardware. this is a precaution necessary to ensure stable dma operation. the table below lists the registers that can or cannot be accessed for write. table 9.4.1 dmac related registers that can or cannot be accessed for write status transfer enable bit transfer request flag other dmac related registers transfer enabled can be accessed can be accessed cannot be accessed transfer disabled can be accessed can be accessed can be accessed even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be observed: (1) dma channel control register 0 transfer enable bit and transfer request flag for all other bits in this register, be sure to write the same data that those bits had before the write. note, however, that only writing "0" is effective for the transfer request flag. (2) dma transfer count register when transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored. (3) rewriting the dma source and dma destination addresses on different channels by dma transfer although this operation means accessing the dmac related registers while dma is enabled, there is no problem. note, however, that no data can be transferred by dma to the dmac related registers on the currently active channel itself. ? manipulating the dmac related registers by dma transfer when manipulating the dmac related registers by means of dma transfer (e.g., reloading the dmac related registers with the initial values by dma transfer), do not write to the dmac related registers on the currently active channel through that channel. (if this precaution is neglected, device operation cannot be guaranteed.) it is only the dmac related registers on other channels that can be rewritten by means of dma transfer. (for example, the dman source address and dman destination address registers on channel 1 can be rewritten by dma transfer through channel 0.) ? about the dma interrupt request status register when clearing the dma interrupt request status register, be sure to write "1" to all bits, except those to be cleared. writing "1" to any bits in this register has no effect, so that they retain the data they had before the write. ? about the stable operation of dma transfer to ensure the stable operation of dma transfer, never rewrite the dmac related registers, except the channel control register?s transfer enable bit, unless transfer is disabled. one exception is that even when transfer is enabled, the dma source address and dma destination address registers can be rewritten by dma transfer from one channel to another. 9.4 precautions about the dmac 9 9-32 dmac 32176 group user?s manual (rev.1.01) this page is blank for reasons of layout. 9.4 precautions about the dmac chapter 10 multijunction timers 10.1 outline of multijunction timers 10.2 common units of multijunction timers 10.3 top (output-related 16-bit timer) 10.4 tio (input/output-related 16-bit timer) 10.5 tms (input-related 16-bit timer) 10.6 tml (input-related 32-bit timer) 10 10-2 multijunction timers 10.1 outline of multijunction timers 32176 group user?s manual (rev.1.01) 10.1 outline of multijunction timers the multijunction timers (abbreviated mjt) have input event and output event buses. therefore, in addition to being used as a single unit, the timers can be internally connected to each other. this capability allows for highly flexible timer configuration, making it possible to meet various application needs. it is because the timers are connected to the internal event buses at multiple points that they are called the ?multijunction? timers. the 32176 has four types of mjt as listed in the table below, providing a total of 37-channel timers. table 10.1.1 outline of mjt name type no. of channels description top output-related 11 one of three output modes can be selected by software. (timer 16-bit timer |